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RSS FeedPython scipy.signal IIR Filtering: An Example
Introduction In the last posts I reviewed how to use the Python scipy.signal package to design digital infinite impulse response (IIR) filters, specifically, using the iir...
posted by Christopher Felton on May 19 2013 under Audio DSP | FPGA | Basics | Tips and Tricks | Python Comments (0) |
A Fixed-Point Introduction by Example
Fixed-point is used to represent fractional numbers of finite-word length. Fixed-point is an interpretation of a 2's compliment number usually signed but not limited to sign representation. &nbs...
posted by Christopher Felton on Apr 25 2011 under FPGA | Basics Comments (13) |
DSP Algorithm Implementation: A Comprehensive Approach
As DSP engineers, ultimately we are required to design and implement specific DSP algorithms. The first step is to make a choice on which algorithm to use, e.g. for filtering should we use FIR or IIR.... 
posted by Sami Al Dalahmah on Apr 13 2011 under FPGA | Design Methodolgies | Verilog Comments (6) |
Half-band filter on Xilinx FPGA
1. DSP48 Slice in Xilinx FPGA There are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending o... 
posted by Lyons Zhang on Nov 30 2010 under FPGA | Verilog Comments (5) |
Instantaneous Frequency Measurement
I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. Bu... 
posted by Parth Vakil on Feb 4 2008 under Matlab | FPGA | Basics Comments (20) |