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Use DSP to implement fractional N PLL

Hi all, I have an integer PLL and DSP in my system, I want fine resolution (a fraction of the PLL step size). Is possible to just use the DSP to adjust the reference frequency instead of using a fractional-N PLL chip? Thanks Guang ...

interaction between bandpass equalizer and pll

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked before the channel is reasonably equalized. Thus, I have a "bootstrap" where the equalizer need phase information(from pll) and the pll need equalized sign...

interaction between bandpass equalizer and pll

Hi, When using the SG algorithm for equalizing, the error signal is computed at the end of the pll. My problem is that the pll cannot be locked before the channel is reasonably equalized. Thus, I have a "bootstrap" where the equalizer need phase information(from pll) and the pll need equalized sign...

MSK demodulation using PLL

Can I implement a MSK demodulator using PLL? Basically I want to demodulate MSK using FM demodulator IC. The IC uses a PLL for FM demodulation. What are the drawbacks in using PLL ( if I can use one ) as compared to coherent demodulator with carrier recovery? Thanks ~ Kaushal ...

Coherent vs Noncoherent GFSK Demodulation

Hi, I've been working on demodulation of low-deviation GFSK signals similar to Bluetooth, with h=0.3 and BT=0.5. I have two simulations, one using a discriminator plus integrate and dump, and another with a second order PLL. I am computing BER vs Eb/No for each case. In the PLL case, I expect...

PLL Basics

Bonjour, I'd like to understand what is globally a bandwidth PLL. I know that a PLL uses in internal low pass filter (numerical). But, if we take a PLL as a black box, in relation with the input reference timing, is it again a low pass filter with just a high cutoff frequency, or a bandpass...

PLL with external feedback at 622.08

Hi All I=92m going to design a PLL for the frequency of 622.08MHz. This PLL should support external feedback. I=92ve looked for such PLL muck but I haven=92t found . What shall I do if such a PLL doesn=92t exist? I know that there is many =93phase and freq. detector=94 and VCXO from different ...

Re: Software PLL (SPLL)

Tim Wescott wrote: > Implementing a PLL in software uses the same basic theory as > implementing a PLL in hardware -- you compare your synthesized signal to > a reference, generate a phase difference, then servo the frequency of > your synthesized signal to your reference. Why? Isn't a s...

Discrete time PLL (Digital PLL, DPLL)

comp.dsp, I need a robust*, free discrete time PLL algorithm, and I haven't had much luck searching the net. Pointers anyone? TIA, Emanuel Landeholm *Must work with reasonably non-sinusoidal signals (harmonic distortion) and reasonably aliased (inharmonic distortion, pseudo periodi...

Re: Software PLL (SPLL)

Ron N. wrote: > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > implementing a PLL in hardware -- you compare your synthesized signal to > > a reference, generate a phase difference, then servo the frequency of > > your synthesized signal to your re...

Re: Software PLL (SPLL)

Terry Given wrote: > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > > implementing a PLL in hardware -- you compare your synthesized signal to > > > a reference, generate a phase difference, then servo the frequency of > > > y...

I-Q vs PLLs

Which gives best performance, a Phase-locked-loop (say all digital - software) or I-Q (ie using arctan and then differentiating) demodulation.Reason I am asking is that a PLL is supposed to be the best - is it better than just the pure number crunching.It woudl appear to me that when you differe...

Re: Loop Bandwidth and PLL understanding

On Oct 8, 7:43=A0am, aizza ahmed wrote: > Hello Everybody, > =A0 =A0 =A0 =A0 =A0Thanks to all experts, i am learning a lot from this g= roup. > after studying good amount of literature, i see that the terminology > Loop Bandwidth is more applicable to Analog PLL. Say in Costal PLL, > t...

Re: Software PLL (SPLL)

In article , Ron N. wrote: > Tim Wescott wrote: > > Implementing a PLL in software uses the same basic theory as > > implementing a PLL in hardware -- you compare your synthesized signal to > > a reference, generate a phase difference, then servo the frequency of > > your synthesized ...

Re: Software PLL (SPLL)

Ron N. wrote: > Terry Given wrote: > > > Ron N. wrote: > > > > > Tim Wescott wrote: > > > > > > > Implementing a PLL in software uses the same basic theory as > > > > implementing a PLL in hardware -- you compare your synthesized signal to > > > > a reference, generate a phase differen...

DDS - PLL hybrid linear sweep synthesizer

Dear professionals, I am interested in designing of a DDS / PLL hybrid linear sweep synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my case the DDS would be able to produce a highly linear frequency chirp from 0 to 400 MHz, but I have to produce an RF chirp of the frequenc...

Digital PLL and FM demodulation

Hello, PLL is a good way to do FM demodulation in analogue domain. What about its use in digital domain? Why not to use a digital PLL to do FM demodulation? what is advantages(if any) and disadvantages of this technique? Regards ...

implementation of PLL

Dear Prof.Wolfgang Thank for your reply about PLL and your suggestions are very good and implementation can be possible.Please suggest what you answer " apply MAC operation to voltage using sin-table" jkm ...

Software PLL

I'm looking for guidance on writing a software PLL for a signal acquired from a data acquisition board: The daq board will be sampling at 10kSPS. The signals to which I'd like to lock on to are from 5Hz to 1kHz, sine or square wave. The output of the PLL will be used to multiply a signal acquired...

Low Pass Filter for a PLL

Hi all. I have done a PLL for tracking frecuency carrier in a MFSK demodulator. I have used a moving filter average of length=64 as low pass filter. I cannot rise lenght more than 64 because then PLL would not track frecuency desviations of the transmitter. I dont know if there are other filt...

Phase ambiguity

Hi all, We know that a Decision-Feedback PLL (DF-PLL) for MPSK signals has a phase ambiguity of 360/M. How can I go about proving that? Thanks for any pointers. ...

PLL to generate low frequencies

Hi, This is my first post to this forum. I have a reference oscillator of 12.7 MhZ, how do I generate the following frequencies using this oscillator 16.863406408094434 Hz 16.722408026755854 16.694490818030051 13.755158184319120 12.562814070351759 12.531328320802006 12.062...

Re: Software PLL (SPLL)

Ken Smith wrote: > In article , > Ron N. wrote: > > Tim Wescott wrote: > > > Implementing a PLL in software uses the same basic theory as > > > implementing a PLL in hardware -- you compare your synthesized signal to > > > a reference, generate a phase difference, then servo the ...

Re: When is a fractional-N PLL needed?

> On Aug 4, 1:23=A0pm, "gretzteam" > wrote: > > Hi, > > I'm trying to understand when a fractional-N PLL is required. I'm doing > > this in an FPGA so it's an ADPLL, but I think my questions are basic enou= > gh > > that it applies to any PLL. > > > > When using a basic PLL topolog...

urgent..c code to implement PLL

hi all, as my project submission date is fast approaching i need c (not c++) code to implement PHASE LOCKED LOOP (PLL) and to plot output graphs..please take the pains to reply this messege with code or even location where can i get that. thanx Patro ...

PLL and AFC

PLL is Phase Lock Loop, while AFC is Automatic Frequency Control. Anyone in the group knows what is the difference between these 2 systems, since both are considered as frequency tracking system for transciever? Why in some application we have to choose AFC? THX a lot. ...

Discrete time PLL - mean time between slips

Hi guys, Can anyone point me to a paper/book describing the analysis of the discrete time PLL? All I could find are books describing the nonlinear analysis of the continuous time PLL -- an analysis that is based on nonlinear differential equations. A discrete time analysis avoids the dif...

FM demod using PLL

I am looking for an example of using a software pll for demod of FM. I tried the other fm demod routines (arctan, differentiator) and think there could be an improvement using a software pll. I found some matlab code posted by Tom ? that works on his data (generated by matlab) but fails on mi...

PLL - quadrature output

Hi Does PLL have a property that under locked state, the output is in quadrature with the reference input ? I know that this is true if the phase detector is of multiplier/mixer type ( using the approximation sin E ~ E for error E. ) I am asking whether the above property is t...

implementation of PLL

I am a research scholar working in Power System related to Power Electronics devices. In my work I have to use PLL through assembly langeage programming (by TMS320LF2407A EVM board in Code Composer 2000 environment) for detecting the instantanous frequency of a 3ph transmission line. any one can...

PLL based Clock

Would someone explain PLL based clock? Phase locked loop Thanks ...

Re: Software PLL (SPLL)

Terry Given wrote: > Ron N. wrote: > > Terry Given wrote: > > > > > Ron N. wrote: > > > > > > > Tim Wescott wrote: > > > > > > > > > Implementing a PLL in software uses the same basic theory as > > > > > implementing a PLL in hardware -- you compare your synthesized signal to ...

PLL noise bandwidth

Hi, Can someone tell me in a few words what does noise bandwidth in a PLL mean and also suggest me book or papers where I can know more about it. I want to write an algorithm for the code tracking loop of a DSSS system and the book 'Software defined GPS and Galileo receiver' that I am referring now...

Question about damping in PLL

Hi, I am learning PLL from a web download PLLTutorialISSCC2004.pdf after I read two books on PLL. I do not understand the following statements from the web pdf: ........................... Less ringing and overshoot as Zeta =3D 1 Severe overdamping --> ringing and overshoot Ringing at hi...

CS8420 (again ;) )

Hi everybody There has been some advice and answers about this old chip, but I would still appreciate some help with a precise functionality it : I must use the CS8420 in a new design in software control mode (to allow writing to the U-block buffer) with an FPGA and I must allow the users to pl...

How to understand the zero of PLL with integral and proportional path

Hi, I am learning PLL from a tutoril. It says the zero has the character, see below. The zero has the transfer function value 0, but I cannot arrive the conclusion below. Could you explain it to me more? Thanks in advance. ..................... The =93Zero=94 in the numerator of the cl...

Phase resolution in PLL at audio frequencies

Hi all. I don't have much background in PLL implementation and would appreciate if someone can refer me to basic info. I need to measure the phase of an unmodulated 15 kHz tone down to 0.1 degree if possible. The tone has decent S/N of about 30-40 dB. For acquisition purposes I know its freq...

Premodulation filter/PLL loop filter

Mayby not the right group, but.. On my bench, I have created an ad-hoc signal generator to drive some old paging receiver boards. I am using a DDS to generate phase-continuous, 4-level FSK. I'm then "multiplying" the output of the DDS (using a PLL/VCO module) by 11, creating an RF carrier...

Achievable threshold extension?

Back several years ago I implemented a DSP based, PLL FM demod for a satellite downlink application. It achieved about 3 to 4 dB of threshold extension over a conventional demod. My question is, can greater extension be achieved using PLL or FMFB techniques in special cases? Specifically, can g...

Digital phase/frequency detector

There is a software PLL with a hardware phase detector. The phase detector is done in that way so it outputs the phase difference (+/- Pi) and the absolute frequency difference at the same time. What could be the best use for the phase and the frequency information in the PLL ? It is desired to ...