TDL for Parallel Processing

When multiplies and additions can be performed in parallel, the computational complexity of a tapped delay line is multiplies and additions, where is the number of taps. This computational complexity is achieved by arranging the additions into a binary tree, as shown in Fig.1.15 for the case .

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written by Julius Orion Smith III
Julius Smith's background is in electrical engineering (BS Rice 1975, PhD Stanford 1983). He is presently Professor of Music and Associate Professor (by courtesy) of Electrical Engineering at Stanford's Center for Computer Research in Music and Acoustics (CCRMA), teaching courses and pursuing research related to signal processing applied to music and audio systems. See http://ccrma.stanford.edu/~jos/ for details.