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Discussion Groups | Analog Devices DSPs | ADSP 218x Architecture questions...
Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).
ADSP 218x Architecture questions... - Khubaib - Jan 18 6:20:00 2003
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Dear members..i am a new member to this group..i have some questions.. i have some VLSI background, and i have recently started developing DSP programs for ADSP-218x processors. It is a single cycle architecture. How can it read/write a location on on-chip RAM in one cycle??. (from MY VLSI background, a RAM read/write takes 2 cycles.)..also, can anybody provide me with the detailed memory configuration of ADSP-2188..??..Also, Is the Instruction Register (IR) there in ADSP-218x...??>.There is also a Program Counter Register (PC) register there. In the presence of these two registers, there is a implicit pipeline stage being created..Then, how the ADSP- 218x manages to test and perform the instruction in the same cycle...?. also, what is the clock rate being used by the ADSP-218x..??...Does the MIPS rating (which is 40 or 75 for many DSPs) is the instruction execution rate or some other benchmarks..???.. What is meant by zero overhead looping which is being acclaimed by ADSP-218x.? Thanx for the help.. Khubaib |
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Re: ADSP 218x Architecture questions... - Kenneth Porter - Jan 18 21:53:00 2003
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--On Saturday, January 18, 2003 6:20 AM +0000 "Khubaib <>" <> wrote: > How can it read/write a location on on-chip RAM in one cycle??. (from > MY VLSI background, a RAM read/write takes 2 cycles.) I'm not real familiar with that part, but the SHARC has dual-ported memory (CPU and I/O simultaneous access) with separate read and write ports, which I guess could be considered quad-ported memory. One of the defining characteristics of the SHARC architecture is its very high memory bandwidth, allowing the CPU to do single-cycle read-modify-write while still performing full-memory-speed I/O (eg. DMA to/from the system being controlled). Further, the 21065L has two banks of memory, so one can do vector MAC's (eg. multi-tap filters) at full speed by pulling instructions and coefficients from one bank and data from another. (Instructions and data can use separate ports on the same bank.) The 2116x doubles this by adding a second ALU, allowing one to split a vector operation between the two ALU's (odd indices to one and even to the other). |
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Re: ADSP 218x Architecture questions... - Ali Irfan Ahmed - Jan 18 22:30:00 2003
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Hi,
How can it read/write a location on on-chip RAM in one cycle??. (from
MY VLSI background, a RAM read/write takes 2 cycles.) The Analog 218x series processor does by clock doubling the
external clock is internally run at 2x speed. On the Rising edge memory is written and on the
falling edge the memory is written. More explanation is in the 218x Hardware
manual.
also, can anybody provide me with the detailed memory configuration of ADSP-2188..??
2188 has 48K of 24 bit program memory and 56k of 16bit data
memory. since the internal register of 218x are 16 bit at one time only 16k of either memories
are accessible. the rest of memory is accessed through overlay register . In case of program
memory the extra memory is overlayed on address beginning from 0x2000 to 0x3fff and in case of
data memory the extra memory is overlayed on address beginning from 0x0000 to
0x1fff.
Instruction Register
(IR) there in ADSP-218x...??>.There is also a
Program Counter Register (PC) register there. In the presence of these two registers, there is a implicit pipeline stage being created..Then, how the ADSP- 218x manages to test and perform the instruction in the same cycle...?. 218x has a PC as all processors have but no pipeline it
prefetches only one instruction and decodes and execute in the next clock. Again refer
manual.
also, what is the
clock rate being used by the ADSP-218x..??...Does
the MIPS rating (which is 40 or 75 for many DSPs) is the instruction execution rate or some other benchmarks..???.. the clock of 218x series is half the Mips(peak). when all
the instructions are multi instructions the dsp performs at its peak mips. since the dsp is
usually used as a co-processor for Algorithms the usual throughput is 75-90% of peak rated
mips.
What is meant by zero
overhead looping which is being acclaimed by
ADSP-218x.? When ever 218x core encounters the loop instruction it saves the loop start address on an internal stack loop along with loop exit condition on the last instruction a comparison is made depending upon the loop terminating condition either the start address of loop is loaded in PC or the next instruction to the end loop instruction is loaded since both address are aprior known no overhead is needed to recalculate the next PC value so there is zero overhead in looping no cycles are wasted or flushing required. All this is explained in 218x Manual with illustrations and
detail. This is a short summary of ur problems. I hope I was of help to you.
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Re: ADSP 218x Architecture questions... - Jeff Brower - Jan 18 23:20:00 2003
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Ali Irfan Ahmed- > The Analog 218x series processor does by clock doubling > the external clock is internally run at 2x speed. On the > Rising edge memory is written and on the falling edge the > memory is written. More explanation is in the 218x Hardware > manual. Texas Inst. emphasis in their C54xx 16-bit fixed-point series appears to be towards adding more internal SRAM, rather than increasing external memory efficiency. For example, C5416 has 128k x 16 onchip SRAM; C5441 has 4x cores, each with 64k x 16 local, and another 512k x 16 shared SRAM between the cores. But these parts are more expensive certainly, and the cheaper ones like C5402 face external memory issues. What's the most onchip memory that a 218x or similar ADI 16-bit fixed-point device has internal? Jeff Brower DSP sw/hw engineer Signalogic |
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Re: ADSP 218x Architecture questions... - twd2950 - Jan 20 22:39:00 2003
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> What's the most onchip memory that a 218x or similar ADI 16-bit fixed-point device > has internal? > Jeff Brower > DSP sw/hw engineer > Signalogic I believe the 2188 has the largest internal memory for the 8x series (48K at 24bit width<program memory> and 56K at 16bit width<data memory>). The 2191 has the largest internal memory for the 9x (32K at 24bit width and 32K at 16bit width) and has the ability to externally address 254 pages of 64KW or 64KB memory (or 256 pages if you change a bit to use BMS~... in order to access page 0/FF off chip rather than on chip). also The instruction pointer on the 9x is 16 bits rather than 14bits... but there isn't a hardware overlay feature.... Tim D |
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Re: Re: ADSP 218x Architecture questions... - Jeff Brower - Jan 21 12:46:00 2003
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Tim- Thanks Tim. Without an overlay mode (C54xx) or remapping feature (563xx), then onchip program memory is limited to 48k for 218x and 32k for 219x. Somehow I thought 219x had more onchip program memory than that. For most of the algorithms (or combinations) we are running, we need 64k minimum. If we were using 8 nsec SRAMs, at what speed can we run these processors and obtain zero wait-state external program memory access? Jeff Brower DSP sw/hw engineer Signalogic "twd2950 " wrote: > > > What's the most onchip memory that a 218x or similar ADI 16-bit > fixed-point device > > has internal? > > Jeff Brower > > DSP sw/hw engineer > > Signalogic > > I believe the 2188 has the largest internal memory for the 8x series > (48K at 24bit width<program memory> and 56K at 16bit width<data > memory>). The 2191 has the largest internal memory for the 9x (32K > at 24bit width and 32K at 16bit width) and has the ability to > externally address 254 pages of 64KW or 64KB memory (or 256 pages if > you change a bit to use BMS~... in order to access page 0/FF off chip > rather than on chip). also The instruction pointer on the 9x is 16 > bits rather than 14bits... but there isn't a hardware overlay > feature.... > > Tim D |
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Re: ADSP 218x Architecture questions... - twd2950 - Jan 23 5:02:00 2003
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Jeff, The nice feature with the 219x is that it uses 16 bits rather than 14 bits for addressing. On the 2191, there is 32K of program memory at 24bit width (0x0000- 0x8000) and 32K of data memory at 16bit width (0x8000-0xFFFF). ADI says 160k bytes of memory on their website (24/8*32K+16/8*32K=160KBYTES). The memory is unified unlike the 8x series. What kind of algorithms are you needing? 64K minimum? of what? If you keep code and data in the DSP you'll run faster. The 2191 has memDMA which allows you do move data from one location to another with a DMA controller. You could use this feature to move data/code in/out of the dsp to/from external memory when needed. I'd have to take a look at the datasheets for both the dsp and the ram your using to determine if you need to insert waitstates. The write and read times are dependent on the clk your using. Whose 8 nsec SRAMS are you using? Check out chp14 and Appendix B of the hardware user's Manual. There should be 5 registers for external memory access control for the waitstates.... ms1ctl ms0ctl ms3ctl ms2ctl bmsctl.. -Extended Write hold -1/2/4/8/16/32 <=wait state counter clk based on some division of the HCLK<= might want to check that in the manual.... -up to 7 wait states for RD and WR... there is a count value for WR and RD that you can use per chip select. Regards, TD --- In , Jeff Brower <jbrower@s...> wrote: > Tim- > > Thanks Tim. Without an overlay mode (C54xx) or remapping feature (563xx), then > onchip program memory is limited to 48k for 218x and 32k for 219x. Somehow I thought > 219x had more onchip program memory than that. For most of the algorithms (or > combinations) we are running, we need 64k minimum. > > If we were using 8 nsec SRAMs, at what speed can we run these processors and obtain > zero wait-state external program memory access? > > Jeff Brower > DSP sw/hw engineer > Signalogic > "twd2950 " wrote: > > > > > What's the most onchip memory that a 218x or similar ADI 16-bit > > fixed-point device > > > has internal? > > > Jeff Brower > > > DSP sw/hw engineer > > > Signalogic > > > > I believe the 2188 has the largest internal memory for the 8x series > > (48K at 24bit width<program memory> and 56K at 16bit width<data > > memory>). The 2191 has the largest internal memory for the 9x (32K > > at 24bit width and 32K at 16bit width) and has the ability to > > externally address 254 pages of 64KW or 64KB memory (or 256 pages if > > you change a bit to use BMS~... in order to access page 0/FF off chip > > rather than on chip). also The instruction pointer on the 9x is 16 > > bits rather than 14bits... but there isn't a hardware overlay > > feature.... > > > > Tim D |
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