Hardware : 21065L - Codec Interface | Analog Devices DSPs

Hi Happy Valentine's Day. i wish to interface a AC97 sound codec to ADSP21065L processor in a multichannel mode( through serial port1). As per ADSP21065L manual the RFS (frame sync for codec) will active for one clock cycle in multichannel mode. One clock period is 81.4nS at 12.288MHz(BIT_CLK frequency). so i think the sync will active for 81.4nS time period only. the required sync active pulse width shows in some of the codec's data sheet as 1.3microS(Typical). But they r not mentioned abt the minimum active pulse width for sync. Is this will make any design/working problems. The AD1819 data sheets provides both typical and minimum pulse width for sync. the minimum is 84.1nS and its digital i/o voltage level is 5Volts. In the AD1819A-ADSP21065L interface manual(AD1819A_21065L.pdf), it is specified that the setup and hold time for AD1819 is relaxed enough to meet the active RFS timing specified in sharc 2106x processors. but i wish to interface with a low power codec which matches the frame active pulse width 81.4nS criteria. The new version of ADSP Codec(AD1885) have 3.3V digital I/O. but the data sheet is not specify the value for minimum active sync requirement. but they specified a typical value for this(1.3microSec). Is this codec is also capable of interfacing with 21065L. If i used a codec of required active sync pulse width of 1.3microsecs(Typ) with ADSP 21065L (in multichannel mode) will make any operational problems.Pls note that AC97 codec samples the frame sync only for the first cycle prior to transmission of the MSB of the TAG Phase time slot. Also i wish to know the propagation delay effect of the codec-21065L interface if the sharc places data at +ve clock edges and samples at -ve clock edges(as per AC97 Spec) of the same clock cycle. In the above mentioned manual(AD1819A_21065L.pdf), both the data drive and samples at -ve edge. Is it have any significance. Consider the RFS is used as frame sync for Codec and the SRCTLx's CKRE bit is set as '0'(samples at -ve edges). When will be the RFS generated - at the +ve edge or -ve edge of the BIT_CLK. If the MFD(at STCTLx reg at multichannel mode) is set as 1. At what time the RFS/TFS will generated. Is it one clock cycle prior to the first cycle of the next frame. pls help me to clarify my doubts.if any of my questions are not clear, pls inform me and help to clarify others. i will clarify them soon. regards ajith

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Hardware : 21065L - Codec Interface - ajith_pc - Feb 14 6:47:00 2003