Sign in
Search adsp
Subscribe to adsp
adsp by Keywords
AD1819 | AD7332 | ADSP-2106 | ADSP-21060 | ADSP-21065L | ADSP-2116 | ADSP-21160M | ADSP-2181 | ADSP-218x | ADSP-219 | ADSP-2199 | ADSP219 | BF531 | BF532 | BF533 | BF535 | Blackfin | FFT | JTAG | LDF | SDRAM | SHARC | SPORT | UART | VDSP++ | VisualDSP
Discussion Groups
Discussion Groups | Analog Devices DSPs | Re: DSP algorithms on FPGA/ASIC
Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).
DSP algorithms on FPGA/ASIC - Pinaki Chanda - Apr 3 15:12:00 2003
|
Hi all, I am looking for some good reference on writing optimized VHDL code for signal processing application. Can anyone give me some reference which talks abt smart ways to implement DSP algorithms in ASIC/FPGA ? Thanks and regards, pinaki _______________________________________________________________________ Odomos - the only mosquito protection outside 4 walls - Click here to know more! http://r.rediff.com/r?http://clients.rediff.com/odomos/Odomos.htm&&odomos&&wn |
|
|
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Re: DSP algorithms on FPGA/ASIC - Martin.J Thompson - Apr 4 7:30:00 2003
|
>Hi all, > I am looking for some good reference on >writing optimized VHDL code for signal processing >application. Can anyone give me some reference >which talks abt smart ways to implement DSP algorithms >in ASIC/FPGA ? You could start by looking at Ray Andraka's website (http://www.andraka.com/) and hang out on comp.arch.fpga (and comp.dsp if you're interested in the DSP theory) Cheers, Martin -- Martin Thompson BEng(Hons) CEng MIEE TRW Conekt Stratford Road, Solihull, B90 4AX. UK Tel: +44 (0)121-627-3569 - |
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Re: DSP algorithms on FPGA/ASIC - Eliahu Friedmann - May 16 14:51:00 2003
|
It is definitely a "smart way". Cheers, Eli Martin.J Thompson wrote: Hi all, I am looking for some good reference on writing optimized VHDL code for signal processing application. Can anyone give me some reference which talks abt smart ways to implement DSP algorithms in ASIC/FPGA ?You could start by looking at Ray Andraka's website (http://www.andraka.com/) and hang out on comp.arch.fpga (and comp.dsp if you're interested in the DSP theory) Cheers, Martin -- PLEASE VISIT US AT THE OUT SOURCING WORLD EXIBITION, LONDON, JUNE 3 - 5, 2003, AT THE ROMANIAN PAVILION NEW TELEPHONE NUMBER of RO HOME ======================================================== The information contained in this e-mail is confidential to Isratech and must not be used or passed to any third party without permission. ======================================================== ASIC Art LTD Meshek 108 Bat Shlomo 30992, ISRAEL Tel: +972 4 639 8608 Fax: +972 4 629 4010 Mobile: +972 52 852 076 ----------------------------------------------------------------------------------------------- - Isratech SRL Splai Bahlui 24, bl C1, sc E, ap 3 Iasi, 6600 ROMANIA Tel: +40 232 219 992 (office) Fax: +40 232 217 852 Tel: +40 232 432 764 (RO home) Mobile: +40 722 402 708 www.isratech.ro ======================================================== |
|
|
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Re: DSP algorithms on FPGA/ASIC - Martin.J Thompson - May 19 8:49:00 2003
|
Eliahu Friedmann <> wrote: > Write the algorithm in Matlab and use AccelChip tool (www.accelchip.com)to move to HDL RTL (Verilog or VHDL) > >It is definitely a "smart way". > >Cheers, >Eli > >Martin.J Thompson wrote: I didn't actually write all that you quoted, an attribution must have got lost there - all I said was >> You could start by looking at Ray >>Andraka's website (http://www.andraka.com/) and hang out on comp.arch.fpga (and comp.dsp if you're interested in the DSP theory) Cheers, Martin |
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Re: DSP algorithms on FPGA/ASIC - Sigmund Gudvangen - May 19 18:14:00 2003
|
Le Vendredi 16 Mai 2003 16:51, Eliahu Friedmann écrivit : > Hi all, > I am looking for some good reference on > writing optimized VHDL code for signal processing > application. Can anyone give me some reference > which talks abt smart ways to implement DSP algorithms > in ASIC/FPGA ? Have a look at: 1) Lars Wanhammar , Dsp Integrated Circuits, Academic Press, 1999. 2) Keshab K. Parhi, VLSI Digital Signal Processing Systems : Design and=20 Implementation, Wiley-Interscience, 1999. Regards Sigmund. |
|
|
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Need your help:FIR FILTER DESIGN using Lookup Tables - Siripon Sukuabol - May 20 3:00:00 2003
|
Dear All; I need your help. I have designed FIR Low Pass Filter using Lookup Table and I have a problem to sum the output coefficients. I do not know how to set up scale accumulator at final result. I have 20 LUT. 0-159 coefficient after add first time and accumulate 1\2 left 10LUT after add second times and accumulate 1\4 left 5LUT I left 3LUT and I do not know how to scale. I attach document file shown about diagram. If anyone know how to solve this problem,please help me. Thank you very much. Regards; Siripon __________________________________ | |||
| |||
|
|
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )
Re: Need your help:FIR FILTER DESIGN using Lookup Tables - Sigmund Gudvangen - May 20 11:46:00 2003
|
Le Mardi 20 Mai 2003 05:00, Siripon Sukuabol écrivit : > Dear All; > > I need your help. > I have designed FIR Low Pass Filter using Lookup Table > and I have a problem to sum the output coefficients. > I do not know how to set up scale accumulator at final > result. > > I have 20 LUT. 0-159 coefficient > after add first time and accumulate 1\2 left 10LUT > after add second times and accumulate 1\4 left 5LUT > I left 3LUT and I do not know how to scale. You are presumably using fixed-point arithmetic, so the sum will grow by one bit (worse case) for each summation. Hence you need to scale, i.e. right-shifting the word by one bit per addition. The scaling can either be distributed (i.e. you shift by one bit after each addition) or you may use wide enough register to accommodate the word-growth and then carry out a multi-bit shift of the final sum. The latter option leads to lower round-off noise, but at the expense of increased area requirements (I presume we are talking about an ASIC or FPGA). However, the best option might be to simply pre-scale the filter coefficient vector. That way you don't need shifters. Regards Sigmund. |
(You need to be a member of adsp -- send a blank email to adsp-subscribe@yahoogroups.com )