Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).
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Hello, We are working in ADSP2191M which is been interfaced with CPLDs and RAMs. The CPLD is mapped to the External IO memory of ADSP2191. We need help in writing code for asserting the pin /IOMS(selecting a logic in the CPLD). The sample code we tried is: ar=0xa0a0; iopg=0x08; io(0x023)=ar; The ADSP2191M is used with the APEX-ICE. Regards, Unmai. |
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At 06:55 AM 5/23/2003, Unmai R.R wrote: >Hello, > >We are working in ADSP2191M which is been interfaced with CPLDs and >RAMs. The CPLD is mapped to the External IO memory of ADSP2191. We need >help in writing code for asserting the pin /IOMS(selecting a logic in the >CPLD). > >The sample code we tried is: > >ar=0xa0a0; >iopg=0x08; >io(0x023)=ar; > >The ADSP2191M is used with the APEX-ICE. > >Regards, >Unmai. IOPG has a one cycle latency. Try this >iopg=0x08; >ar=0xa0a0; >io(0x023)=ar; Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com |