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Discussion Groups | Analog Devices DSPs | (No Subject)
Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).
(No Subject) - Steve Holle - Dec 15 18:25:00 2003
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I'm using an ADSP-21065L in conjunction with an AD73322L CODEC. I'm
using chained DMA with an interrupt generated at the boundaries of each
DMA Tx and Rx block. I do a minimal amount of processing in each
interrupt, never disabling interrupts. When I compile for Debug, the code works fine. If I compile for release the code runs for 3-5 seconds and then quits generating Rx and Tx interrupts. The AD73322L is still generating the SCLK and FS signals but no more interrupts occur. I also noticed that the DMATX1A and DMARX1A C and CP registers are still changing each time I restart and halt the processor. It seems like the Interrupt is being missed. Any ideas? Steve Holle Link Communications, Inc. 1035 Cerise Road Billings, Montana 59101-7378 406.245.5002 s...@link-comm.com -------------------------- |
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Re: - Mike Rosing - Dec 15 19:01:00 2003
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On Mon, 15 Dec 2003, Steve Holle wrote: > I'm using an ADSP-21065L in conjunction with an AD73322L CODEC. I'm using > chained DMA with an interrupt generated at the boundaries of each DMA Tx > and Rx block. I do a minimal amount of processing in each interrupt, never > disabling interrupts. > > When I compile for Debug, the code works fine. If I compile for release > the code runs for 3-5 seconds and then quits generating Rx and Tx > interrupts. The AD73322L is still generating the SCLK and FS signals but > no more interrupts occur. I also noticed that the DMATX1A and DMARX1A C > and CP registers are still changing each time I restart and halt the > processor. It seems like the Interrupt is being missed. > > Any ideas? The main thing I've seen when that happens is that the debug mode is zeroing out a bunch of register or memory locations, and the release mode isn't. Go thru every register associated with the dma, interrupt and i/o port and make sure they get set to 0, then hit your code. If nothing else you'll find every thing to check! Patience, persistence, truth, Dr. mike |
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(No Subject) - andor_bariska - Dec 16 10:57:00 2003
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Steve Holle wrote: ... > When I compile for Debug, the code works fine. If I compile > for release the code runs for 3-5 seconds and then quits > generating Rx and Tx interrupts. The AD73322L is still > generating the SCLK and FS signals but no more interrupts occur. > I also noticed that the DMATX1A and DMARX1A C > and CP registers are still changing each time I restart and halt > the processor. It seems like the Interrupt is being missed. Steve, 1. If it works in Debug configuration, why bother with the Release configuration? 2. If there is additional stuff declared in Release configuration, what is it? Regards, Andor |
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Re: (unknown) - Steve Holle - Dec 16 15:19:00 2003
At 03:57 AM 12/16/2003, andor_bariska wrote:Steve Holle wrote: It bothers me that something in the code reacts differently with optimization on. I may well need optimization later as the code becomes more complex. 2. If there is additional stuff declared in Release configuration, I don't have any code that is dependant on the Release configuration, if that is what you mean. Regards, Steve Holle Link Communications, Inc. 1035 Cerise Road Billings, Montana 59101-7378 406.245.5002 s...@link-comm.com -------------------------- |
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Re: (unknown) - Author Unknown - Dec 16 16:54:00 2003
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Steve Holle wrote: > At 03:57 AM 12/16/2003, andor_bariska wrote: > >Steve Holle wrote: > >... > > > When I compile for Debug, the code works fine. If I compile > > > for release the code runs for 3-5 seconds and then quits > > > generating Rx and Tx interrupts. The AD73322L is still > > > generating the SCLK and FS signals but no more interrupts occur. > > > I also noticed that the DMATX1A and DMARX1A C > > > and CP registers are still changing each time I restart and halt > > > the processor. It seems like the Interrupt is being missed. > > > >Steve, > > > >1. If it works in Debug configuration, why bother with the Release > >configuration? > > It bothers me that something in the code reacts differently with > optimization on. I may well need optimization later as the code > becomes more complex. OK. It wasn't clear that you had optimization turned on for debug and turned off for release configuration. I think somebody else already had that problem on the 65L - check the archive. > >2. If there is additional stuff declared in Release configuration, > >what is it? > > I don't have any code that is dependant on the Release > configuration, if that is what you mean. Yup, that's what I meant. I use debug for simulation and release for the target hardware development so the two codes are never identical for me. Regards, Andor |
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Re: - Steve Holle - Dec 16 23:09:00 2003
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I zeroed out the suggested registers and it seems to be running
great. Thanks for the help. At 12:01 PM 12/15/2003, Mike Rosing wrote: The main thing I've seen when that happens is that the debug mode is Steve Holle Link Communications, Inc. 1035 Cerise Road Billings, Montana 59101-7378 406.245.5002 s...@link-comm.com -------------------------- |
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