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Discussion Groups | Analog Devices DSPs | BF532, problem accessing external interface HELP !!!!

Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).

  

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BF532, problem accessing external interface HELP !!!! - Author Unknown - Dec 5 7:29:00 2004





BF532, I made my own board. Boot from SPI.
I'm new to BF.
In C, I can write to external SRAM, but not read. In Assembly, I can
read & write. What did I possibly do or not do that create this
problem? Below is code in C & Assembly that I use to test the read &
write.
Thanks.
=================================

tmp = *pEBIU_AMGCTL;
*pEBIU_AMGCTL = tmp | 0xE; //enable all AMS banks
*pEBIU_AMBCTL1 = 0x2F422F42;

pnt = (unsigned short *)0x2035A5A0; //ams3
ptr = (unsigned short *)0x202A5A50; //ams2

val1=0x5A5A;
val2=0xA5A5;
while (1)
{
*pnt = val1;
val2 = *ptr;
//*ptr = val2;
}

I checked it with a logic analyzer, only write showed up, it never
read (AMS2 stay high, AOE stay high; if I comment out the read, the
result was EXACTLY the same on logic analyzer; meaning AMS3 & AWE
high period & low period were the same).

It weird that write was perfectly fine; address, control signals,
data were correct.

Then I tried it in assembly, both read & write were OK.
p0.l = lo(EBIU_AMGCTL);
p0.h = hi(EBIU_AMGCTL);
r0 = [p0];

r1.l = 0xE;
r1.h = 0x0;
r0 = r0 | r1;
[p0] = r0;
p0.l = lo(EBIU_AMBCTL1);
p0.h = hi(EBIU_AMBCTL1);
r0.l = lo(0x22422242);
r0.h = hi(0x22422242);
[p0] = r0;

p0.l = 0xAAAA;
p0.h = 0x2030;

r3.l = 0xAAAA;
r3.h = 0x5555;
ures:
w[p0] = r3.l;
ssync;
w[p0] = r3.h;
ssync;
jump ures;

=====================================




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Re: BF532, problem accessing external interface HELP !!!! - Eddi...@Yahoo - Dec 6 1:34:00 2004


Hi, you might need to insert csync() before continuous
memory access, like

while (1)
{
*pnt = val1;
csync();
val2 = *ptr;
csync();
//*ptr = val2;
} --- 的訊息： >
> BF532, I made my own board. Boot from SPI.
> I'm new to BF.
> In C, I can write to external SRAM, but not read. In
> Assembly, I can
> read & write. What did I possibly do or not do that
> create this
> problem? Below is code in C & Assembly that I use to
> test the read &
> write.
> Thanks.
> =================================
>
> tmp = *pEBIU_AMGCTL;
> *pEBIU_AMGCTL = tmp | 0xE; //enable all AMS banks
> *pEBIU_AMBCTL1 = 0x2F422F42;
>
> pnt = (unsigned short *)0x2035A5A0; //ams3
> ptr = (unsigned short *)0x202A5A50; //ams2
>
> val1=0x5A5A;
> val2=0xA5A5;
> while (1)
> {
> *pnt = val1;
> val2 = *ptr;
> //*ptr = val2;
> }
>
> I checked it with a logic analyzer, only write
> showed up, it never
> read (AMS2 stay high, AOE stay high; if I comment
> out the read, the
> result was EXACTLY the same on logic analyzer;
> meaning AMS3 & AWE
> high period & low period were the same).
>
> It weird that write was perfectly fine; address,
> control signals,
> data were correct.
>
> Then I tried it in assembly, both read & write were
> OK.
> p0.l = lo(EBIU_AMGCTL);
> p0.h = hi(EBIU_AMGCTL);
> r0 = [p0];
>
> r1.l = 0xE;
> r1.h = 0x0;
> r0 = r0 | r1;
> [p0] = r0;
> p0.l = lo(EBIU_AMBCTL1);
> p0.h = hi(EBIU_AMBCTL1);
> r0.l = lo(0x22422242);
> r0.h = hi(0x22422242);
> [p0] = r0;
>
> p0.l = 0xAAAA;
> p0.h = 0x2030;
>
> r3.l = 0xAAAA;
> r3.h = 0x5555;
> ures:
> w[p0] = r3.l;
> ssync;
> w[p0] = r3.h;
> ssync;
> jump ures;
>
> ===================================== >
> _____________________________________
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>
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