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Discussion Groups | Analog Devices DSPs | Re: Sharc 21065L mulitprocessor and SDRAM

Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).

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Sharc 21065L mulitprocessor and SDRAM - Author Unknown - Nov 3 11:08:00 1999

Hello everybody, I have set up two Sharc 21065L in a multiprocessor enviroment. If they get their code from the external SDRAM, there is a problem with the switching of bus mastership. One DSP is retaining mastership for over 15 microseconds. But I set up the processors to release the bus every 0.3 us if the other processor is requesting the bus by setting up a bmax value. Has anybody had similar problems? Are there some hinds around? Dieter * STN ATLAS Elektronik GmbH *

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Re: Sharc 21065L mulitprocessor and SDRAM - Jkumar - Nov 4 6:23:00 1999

Hi, What you have done with CPA signal? Ofcourse you can play around BMAX value, but it is not good solution. If you give some more info aout the way you had used Bus Arbitration, we may able to help you. ..jk Singaram.Jayakumar phone: 080-5283788 On Wed, 3 Nov 1999 wrote: > Hello everybody, > I have set up two Sharc 21065L in a > multiprocessor enviroment. If they get their code > from the external SDRAM, there is a problem with > the switching of bus mastership. > One DSP is retaining mastership for over 15 > microseconds. But I set up the processors to > release the bus every 0.3 us if the other > processor is requesting the bus by setting up a > bmax value. > > Has anybody had similar problems? > Are there some hinds around? > > Dieter > > * STN ATLAS Elektronik GmbH * > ------------------------------------------------------------------------ > -- Talk to your group with your own voice! > -- http://www.egroups.com/VoiceChatPage?listName=adsp&m=1

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Re: Sharc 21065L mulitprocessor and SDRAM - Author Unknown - Nov 4 14:23:00 1999

Hi, we ran two programs executing an infinte loop from external memory. The CPA signals of both processors are connected. To my knowledge this has only an effect for DMA transfers. Indeed we disabled all interrupts and DMA. The only transfer taking place is the transfer of program words from the external 32 bit SDRAM. We expected to see the bus mastership change every 2 * bmax * internal clock. But after two or a little bit more changes of bus mastership, one processor will no longer release its ~BR line for over 15 us. The time will vary if the SDRDIV (refresh counter of the SDRAM) is changed. If you send your email address to , I can supply bitmaps of the timing diagrams. Regards Dieter

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