Hi

I am trying to build a multiprocessor interface  for TS201 processor using shared memory. To
satify mutual exclusion of resources used by all processor, I need to use bus lock feature of
TS201 processor. But I have an intersting observation while developing this interface:
1- assume that P0 has already locked the bus
2- P1 tries to lock bus and therefore sets buslk active bit 
3- P0 releases bus
4- bus lock interrupt is received by P1

At step 4, I expect that P1 should be bus master but this not the case for all the time. Even
if P1 receives buslk interrupt, P0 is seen as bus master in SYSSTAT register, and then after a
very short time period polling of SYSTAT register, P1 becomes bus master as expected.

What sould be the possibe cause of this problem?
Not: This problem is observed in EZKIT for TS201
Berkant AKIN
www.berkantakin.com

Hello Berkant,

When BUSLK is set, the bus is locked by the requesting processor and buslock interrupt is
received.
This may not be immediately giving control of the bus to requesting processor.
The current master completes all its pending transactions ( transactions that have begun
executing on the cluster bus) 
before relinquishing the bus. 

You need to always check whether the requesting processor has got the mastership by using IF BM
instruction.

Satish Godbole

  ----- Original Message ----- 
  From: Berkant 
  To: a...@yahoogroups.com 
  Sent: Saturday, August 25, 2007 2:14 AM
  Subject: [adsp] Bus Lock in TS201

  Hi

  I am trying to build a multiprocessor interface  for TS201 processor using shared memory. To
satify mutual exclusion of resources used by all processor, I need to use bus lock feature of
TS201 processor. But I have an intersting observation while developing this interface:

  1- assume that P0 has already locked the bus

  2- P1 tries to lock bus and therefore sets buslk active bit 

  3- P0 releases bus

  4- bus lock interrupt is received by P1

  At step 4, I expect that P1 should be bus master but this not the case for all the time. Even
if P1 receives buslk interrupt, P0 is seen as bus master in SYSSTAT register, and then after a
very short time period polling of SYSTAT register, P1 becomes bus master as expected.

  What sould be the possibe cause of this problem?

  Not: This problem is observed in EZKIT for TS201

  Berkant AKIN

  www.berkantakin.com