Hi,

I'm tryin to interface the BF561 chip with the PLX PCI9056 accelerator. What  I know is that
the BF561 is a master only for its local bus while the 9056 can be both a master as well as
slave for its local bus. To interface these two, they have been connected to an FPGA.

Now, by default both should be connected, ie, the BF561 should be connected to 9056. This is
the default and power-up condition. For this I need to drive the LHOLD, LHOLDA, ADS# apart from
the address/data and other signals. I need to know how these signals should be driven. 

The next scenario is when the BF561 wants to use its local bus to access other devices. I think
it will assert its BR# and wait for BG#. In this case, when BF asserts BR# should  I assert the
LHOLD to the PCI9056 and when 9056 asserts LHOLDA should I assert the BG# for the BF561? Will
this be enough for the BF to gain ownership of its bus and access other devices?

Are there any other considerations other than timing and the above to interface both these
chips?