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Discussion Groups | Analog Devices DSPs | Processor state after RESET is pressed..................

Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).

  

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Processor state after RESET is pressed.................. - malli_1729 - Dec 22 10:31:29 2007



I have a basic doubt.........

Listing 3-1. Entering User Mode from Reset
P1.L =3D START ; /* Point to start of user code */
P1.H =3D START ;
RETI =3D P1 ;
RTI ; /* Return from Reset Event */
START : /* Place user code here */
when we are booting after reset this code will put the processor into=20
user mode...................
my doubt is when booting where this code wil reside............after=20
booting is over then only this come into effect then RTI and RETI are=20
not needed directly we can put the code.. ...

Iam toomuch confused about this:

Before if it should be executed means where this code will reside=20
when iam switched on the processor or hardware reset all the things
(memory) will not store any values.....

regarding that iam giving these details:

>From hardware manual:

"A HARDWARE-INITIATED RESET RESULTS in a system-wide reset that=20
includes both core and peripherals. After the RESET pin is=20
deasserted, the processor ensures that all asynchronous  peripherals=20
have recognized and completed a reset. After the reset, the processor=20
transitions into the BOOT MODE SEQUENCE CONFIGURED by the BMODE state.
"

The BOOTMODE sequence is ..........

"The On-Chip Boot Rom located at 0xEF00 0000..
On-Chip Boot ROM Flow
1. Set up Supervisor Mode (doesn=E2=80=99t apply for bypass mode)=20
 	=E2=88' Exits the Reset ISR and uses IVG15 (lowest priority=20
           interrupt)
2. Check to see if this boot request was from a software reset
=E2=88' Check bit 4 of the Reset Configuration Register"

"Normal processing begins in Supervisor mode from the Reset state.=20
Deasserting the RESET signal switches the processor from the Reset=20
state to Supervisor mode where it remains until an emulation event or=20
Return instruction occurs to change the mode. Before the Return=20
instruction is issued, the RETI register must be loaded with a valid=20
return address............."

my doubt is :
when the processor is booting......after reset it will initialise all=20
asynchronous peripherals and went to reset EVT there i have seen=20
0xEF00 0000 so, it will go to on-chip boot kernel....
then the on-chip boot kernel will come out of the reset ISR by=20
issuing RTI and then Configuring the peripheral based on the=20
bootmode....then it will complete the boot process....after it will=20
go to 0xffa0 0000 for BF533..and the application code will be=20
executed...........
Is this is the correct way it will work...

=20


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