Hi,
I am working with Blackfin processor BF534.........
I am configuring three timers in the PWM_OUT mode.... I am mapping three timers to three
separte interrupt Service routines as shown below.............I have intialized all the Timers
in PWM_OUT, PULSE_HI=0, IRQ_ENA=PERIOD_CNT=1.........
void Init_Interrupts()

{
// assign core IDs to interrupts
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffffff;
*pSIC_IAR2 = 0xf4ffffff; /////Timer3 ISR-->IVG11
*pSIC_IAR3 = 0xfffff5f6; /////Timer7 ISR-->IVG12////Timer5 ISR-->IVG13//

// assign ISRs to interrupt vectors
register_handler(ik_ivg11, Timer3_ISR); // Timer3 ISR -> IVG 11
register_handler(ik_ivg12, Timer7_ISR); // Timer7 ISR -> IVG 12
register_handler(ik_ivg13, Timer5_ISR); // Timer5 ISR -> IVG 13

// enable Timer0 interrupt
*pSIC_IMASK |= IRQ_TIMER3|IRQ_TIMER5|IRQ_TIMER7;

ssync();
}
I have written Individual ISR's for all the three timers as given below......

EX_INTERRUPT_HANDLER(Timer3_ISR)
{

*pTIMER_DISABLE =0x0008;
ssync();
// confirm interrupt handling///
*pTIMER_STATUS |= 0x00000008;//------------------------->>(1)
ssync();
printf(" Interrupt 3 occured \n");
ssync();

}

EX_INTERRUPT_HANDLER(Timer7_ISR)
{

*pTIMER_DISABLE =TIMDIS7;
ssync();
// confirm interrupt handling///
*pTIMER_STATUS |= 0x00080000;------------------------->>(2)
ssync();
printf(" Interrupt 7 occured \n");
ssync();

}
EX_INTERRUPT_HANDLER(Timer5_ISR)
{
*pTIMER_DISABLE =TIMDIS5;
ssync();

// confirm interrupt handling///
*pTIMER_STATUS |= 0x00020000;------------------------->>(3)
ssync();
printf(" Interrupt 5 occured \n");
ssync();

}

My problem is based on the equations 1, 2 and 3........After the timer counter reaches the
value of the timer period register, it jumps to the ISR........In the ISR, I am clearing the
TIMILx bit of the particular timers by writing (WIC) to TIMER_STATUS registers.....But the
interrupt bit is cleared (Particular TIMILx bit becomes zero on writing 1 to that bit(wruite 1
to clear)) only in Equation (1)....but not in equation (2) and (3).......Can you suggest the
remedy for my problem.......

Regards,
Nithin K S

PS: Can I use the three different ISR's for three timers....?or should i map the three timers
into same ISR......

------------------------------------

I have not played with the Blackfin yet, but the manual makes this
confusing to me.  The IVG interrupts are general - they are not tied
to the timer.  Since you are using the PWM pulses to generate the
interrupts, you only need to clear the IVG interrupt bits to let the
processor know that interrupt has been dealt with.  There should be
no reason to mess with the timer in the IVG isr handlers.

If you want the interrupts to be continuous, you would not turn off
the timers anyway - just let them continue to generate the interrupt
pulses.

But I haven't dealt with this monster yet either, so I could be totally
wrong!!

Patience, persistence, truth,
Dr. mike

On Wed, 16 Apr 2008 i...@gmail.com wrote:

>  Hi,
> I am working with Blackfin processor BF534.........
> I am configuring three timers in the PWM_OUT mode.... I am mapping three timers to three
separte interrupt Service routines as shown below.............I have intialized all the Timers
in PWM_OUT, PULSE_HI=0, IRQ_ENA=PERIOD_CNT=1.........
> void Init_Interrupts()
>
> {
> // assign core IDs to interrupts
> *pSIC_IAR0 = 0xffffffff;
> *pSIC_IAR1 = 0xffffffff;
> *pSIC_IAR2 = 0xf4ffffff; /////Timer3 ISR-->IVG11
> *pSIC_IAR3 = 0xfffff5f6; /////Timer7 ISR-->IVG12////Timer5 ISR-->IVG13//
>
> // assign ISRs to interrupt vectors
> register_handler(ik_ivg11, Timer3_ISR); // Timer3 ISR -> IVG 11
> register_handler(ik_ivg12, Timer7_ISR); // Timer7 ISR -> IVG 12
> register_handler(ik_ivg13, Timer5_ISR); // Timer5 ISR -> IVG 13
>
> // enable Timer0 interrupt
> *pSIC_IMASK |= IRQ_TIMER3|IRQ_TIMER5|IRQ_TIMER7;
>
> ssync();
> }
> I have written Individual ISR's for all the three timers as given below......
>
> EX_INTERRUPT_HANDLER(Timer3_ISR)
> {
>
> *pTIMER_DISABLE =0x0008;
> ssync();
> // confirm interrupt handling///
> *pTIMER_STATUS |= 0x00000008;//------------------------->>(1)
> ssync();
> printf(" Interrupt 3 occured \n");
> ssync();
>
> }
>
> EX_INTERRUPT_HANDLER(Timer7_ISR)
> {
>
> *pTIMER_DISABLE =TIMDIS7;
> ssync();
> // confirm interrupt handling///
> *pTIMER_STATUS |= 0x00080000;------------------------->>(2)
> ssync();
> printf(" Interrupt 7 occured \n");
> ssync();
>
> }
> EX_INTERRUPT_HANDLER(Timer5_ISR)
> {
> *pTIMER_DISABLE =TIMDIS5;
> ssync();
>
> // confirm interrupt handling///
> *pTIMER_STATUS |= 0x00020000;------------------------->>(3)
> ssync();
> printf(" Interrupt 5 occured \n");
> ssync();
>
> }
>
> My problem is based on the equations 1, 2 and 3........After the timer counter reaches the
value of the timer period register, it jumps to the ISR........In the ISR, I am clearing the
TIMILx bit of the particular timers by writing (WIC) to TIMER_STATUS registers.....But the
interrupt bit is cleared (Particular TIMILx bit becomes zero on writing 1 to that bit(wruite 1
to clear)) only in Equation (1)....but not in equation (2) and (3).......Can you suggest the
remedy for my problem.......
>
> Regards,
> Nithin K S
>
> PS: Can I use the three different ISR's for three timers....?or should i map the three
timers into same ISR......
>

------------------------------------