Multiple 16bit SDRAM issue | Analog Devices DSPs

Technical discussions related to Analog Devices DSPs (including Blackfin, TigerSHARC, SHARC and ADSP-21xx DSPs).

I am working in custom designed BF561 board. I need a help in SDRAM
control=
ler(SDC).

In my board, two 16bit SDRAM (MT48LC8M16A2 =96 2 Meg x 16 x 4 banks) are in=
terfaced with bank0(SMS0) of SDC.
SDQM0 and SDQM1 pins are connected to the DQML and DQMH pins of SDRAM1 resp=
ectively. And the SDQM2 and SDQM3 pins are connected to the DQML and DQMH p=
ins of SDRAM2 respectively. SMS0 pin is connected to CS of both SDRAM1 and =
SDRAM2.

I have configured the SDRAM registers with the following manner,
	*pEBIU_SDBCTL =3D 0x00000013;
	*pEBIU_SDRRC =3D  0x00000613;
	*pEBIU_SDGCTL =3D 0x00D10159;

In my application, i used to store the 32bit value in SDRAM memory location=
.
example:

	#define		START_ADDR	0x00801004
	unsigned int *pBuffer ;
	unsigned int nData =3D 10 ;

	pBuffer =3D (unsigned int*) START_ADDR ;

	*pBuffer =3D nData ;

In above example, the value 10 is stored properly in the 0x00801004 memory =
location. But the same value is also stored in the 0x00801404 memory locati=
on. This is because of all the SDQM[3:0] pins are enabled through EBIU_SDGC=
TL register(From BF561 hardware reference manual).
Q1. Is there any other way to configure/change the state of SDQM pins in BF=
561?

Q2. Is there any problem in hardware interface? (i.e. Interfacing two 16bit=
 chip in same SDRAM bank(SMS0)).
Regards,
palz

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Discussion Groups | Analog Devices DSPs | Multiple 16bit SDRAM issue

Multiple 16bit SDRAM issue - palani_andavan - Nov 21 9:34:04 2009