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Discussion Groups | TMS320C3x | doubts:320c30
Technical discussions about the TI C3x DSPs (including the C31, C32 and C33 DSPs).
doubts:320c30 - Vijay Chandavarkar - Jul 25 4:46:00 2001
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hello all, I have gone through the TMS320C3X manual. My doubts are:- 1. "In the TMS320C30 pipeline, Is the register read is considered as a seperate 'READ' cycle or whether register read occurs at the 'EXECUTION' stage." because if you refer the 320c3x user's manual (p8-8 and 8-19), it has been mentioned that 'ARs Read' under the read cycle. so does it mean that registers 'ARs' are read OR the memory location pointed by 'ARs' are read. 2. In the 3 operand instruction memory reads, if 'SRC1' is in Internal memory and 'SRC2' is in external memory then two memory reads are completed in a single cycle. But, if 'src1' is in external memory and 'src2' is in internal memory then it takes 2 cycles to complete two reads. How is this, if we just interchange the src1 and src2, possible? please refer to 320c3x user's manual(p8-25,26). Thanks in advance __________________________________________________ |
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