Boot | C31 | TMS320VC33 | VC33

Hi  all,
How many instruction cycle does a ldi instruction require?

 I measured a "ldi" instruction cycle with two ways: by accessing
timer
counter memory address and by using the profiling capability of code
composer.

 By accessing timer counter memory address; I accessed the address 00100024h
from the program  and calculate the difference of the counter before and
after "ldi".I got a result of 4 counter increment per
"ldi".

 By using the profiling capability of code composer obtained 8 cycles per
second.
But the user guide says ldi require only one instruction cycle.Please let me
know why I am getting 4,8 instead of 1??

Regards,
Sooraj.

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Sooraj,

The answer is probably wait states.

Regards,
Bill 

> -----Original Message-----
> From: c...@yahoogroups.com [mailto:c...@yahoogroups.com] On 
> Behalf Of Sooraj S
> Sent: Wednesday, March 04, 2009 12:16 AM
> To: c...@yahoogroups.com
> Subject: [c3x] ldi instruction cycle
> 
> Hi  all,
> How many instruction cycle does a ldi instruction require?
> 
>  I measured a "ldi" instruction cycle with two ways: by 
> accessing timer
> counter memory address and by using the profiling capability of code
> composer.
> 
>  By accessing timer counter memory address; I accessed the 
> address 00100024h
> from the program  and calculate the difference of the counter 
> before and
> after "ldi".I got a result of 4 counter increment per
"ldi".
> 
>  By using the profiling capability of code composer obtained 
> 8 cycles per
> second.
> But the user guide says ldi require only one instruction 
> cycle.Please let me
> know why I am getting 4,8 instead of 1??
> 
> Regards,
> Sooraj.

_____________________________________

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Hi Sooraj,

all asm instructions take 4 clock cycles due to 4-step pipeline (fetch,
decode, read, execute). this pipeline is to overlap cpu operations over a
sequential implementation but if you only see the flow of execute step it
seems that any instruction is performed in 1 clock cycle. BRs are
exceptions, the next instruction after any br is executed 4 clock cycles
after because pipeline was flushed.

On Tue, Mar 3, 2009 at 11:15 PM, Sooraj S <s...@gmail.com> wrote:

>   Hi all,
>
> How many instruction cycle does a ldi instruction require?
>
> I measured a "ldi" instruction cycle with two ways: by accessing
timer
> counter memory address and by using the profiling capability of code
> composer.
>
> By accessing timer counter memory address; I accessed the address
00100024h
> from the program and calculate the difference of the counter before and
> after "ldi".I got a result of 4 counter increment per
"ldi".
>
> By using the profiling capability of code composer obtained 8 cycles per
> second.
>
> But the user guide says ldi require only one instruction cycle.Please let
> me
> know why I am getting 4,8 instead of 1??
>
> Regards,
> Sooraj.
>
>  
>

_____________________________________

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