A question about DMA-McBSP configuration~ | TMS320C54x

Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).

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Hello~ groups~~ I have a question about DMA-McBSP configuration. Let me explain some cases. The system that I ponder on has 3 McBSP(each including tx, rx) and 32 multichannels at each. The system has to process Time-switching by connecting each channel. (For example, 0 McBSP-30 timeslot <-> 1 McBSP-5 timeslot, 0 McBSP-15 timeslot <-> 1 McBSP-6 timeslot, and so on.) At the time to appear DMA rx interrupt, functions that should be implented are as follows. After writing 32 data(which are from 32 channels) from McBSP DRR via DMA at memory buffer(i.e MCBSP RX BUF) completely, I have to load the 32 data which had been received at appropriate memory buffer(i.e MCBSP TX BUF), and the memory data are transmitted to McBSP DXR via DMA. After 125us (next DMA rx interrupt), the same work have to be processed. How can I design DMA addressing mode(either multiframe mode or ABU mode) and memory allocation efficienty in the aspect of memory resource? Could you explain the way to switch the channels concretely, please? I am looking forward to hearing from you. Gracious~~!!! HyungJune Lee

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Discussion Groups | TMS320C54x | A question about DMA-McBSP configuration~

A question about DMA-McBSP configuration~ - abbado78 - Dec 6 5:44:00 2002