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Discussion Groups | TMS320C54x | Strange '5402 Timing results
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
Strange '5402 Timing results - Brian C. Lane - Aug 12 0:58:00 2000
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I've got a problem with a TMS320C5402 project that's about to drive me bonkers! In summary my problem is that with my filter coefficients in different places in RAM my filter loop runs at different speeds. Has anyone had similar problems, and what's the solution? More specifically: CLK is 12.288MHz Internal PLL x8 = 98.304MHz Cycle time = 10.17nS The test loop: BK = #127 AR2 = data(*(lplm_ptr)) A = #0 XF = 1 repeat(#126) macp(*AR2+%,LP3000,A) XF = 0 lplm_ptr points to a data buffer aligned on a 0x80 boundary LP3000 is 127 data words of coefficients for the FIR filter, not aligned to anything. Looking at the XF line on the scope I see 2.7uS instead of the 1.3uS I calculate (127 x 10.17nS). Now, if I replace the LP3000 reference with a constant like #2000h it speeds up to 1.3uS! If I set the constant to the location of my LP3000 coefficients (#17B8h) it runs at 2.7uS. If I move my LP3000 coefficients into a memory segment allocated at 3000h it runs at 1.3uS. Aligning the LP3000 location on different boundaries doesn't seem to effect anything. What gives? This is running from within a 48kHz codec interrupt, so nothing else is interrupting it. It is executing 100% in internal RAM, there is no external data bus on this project. The data bus is disabled and the I have the wait states set to 0 (not that it matters, there isn't anything external to access). Has anyone else seen anything like this? I've been using this '5402 for over a year now, and quite frankly its a pain in the ass to get it to work the way you want it to. Any help, advice, prayers, etc. would be greatly appreciated! Brian ----------------------------------------------------- Brian C. Lane Programmer www.shinemicro.com RF & Microcontroller Design |
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Re: Strange '5402 Timing results - Scott Barnes - Aug 12 15:42:00 2000
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Brian, The '5402 has two banks of DARAM, one starting at 0000h and the other starting at 2000h. There are often penalties of one to two cycles if the CPU tries to do too many operations at a time in one bank. I would suggest reading the cycle timing information for MACP very carefully, including all the footnotes. You will probably need to move some coefficients between banks. Good luck! -- Scott |
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