Sign in
Search c54x
Subscribe to c54x
c54x by Keywords
5409 | 5416 | AD5 | ADC | BIOS | Boot | Booting | Bootloader | C540 | C5402 | C5409 | C5416 | CCS | Codec | DMA | Dmad | DSK | DSKPlus | Dsplib | EVM | FFT | FIR | Flash | GPIO | HPI | Initialization | Interrupt | JTAG | LOG_printf | MCBSP | RFFT | RTDX | Sampling | STLM | UART | VC540
Discussion Groups
Discussion Groups | TMS320C54x | 20 BPF? where to find doc's that talk about that?
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
20 BPF? where to find doc's that talk about that? - dsp_man_c54 - Apr 4 19:06:00 2003
|
HI Doni and All, Where did you find the infomation about the 8 bit serial (non spi) stating a 20 BPF rate? I have read all the doc's on C54x, bootloader, and any other referance I could find. the only thing I have seen about that is the bootloader doc states a min 40 cpu cycles between frames? I dont question if 20 bits per frame will work, just that it is a fixed number compared to 40 cpu cycles which could happen in two BCLKR's or some much less than 20BPF. I hope to figure out what I have not understood. When I do I will let the group know of my findings. Maybe someone else will be able to make use some day of those findings. Caleb Austin |
|
|
(You need to be a member of c54x -- send a blank email to c54x-subscribe@yahoogroups.com )
Re: 20 BPF? where to find doc's that talk about that? - Doni Dewantono - Apr 4 21:08:00 2003
|
You're right, my calculation was based on: BLCKR = 1/2 CPUCLK BFSR = 1/40 CPUCLK ------------------- 1 FRAME = 20 BPF Indeed, if BCLKR is very slow you don't need to have a minimum frame of 20 BPF. --- In , "dsp_man_c54" <austca@b...> wrote: > HI Doni and All, > > Where did you find the infomation about the 8 bit serial (non spi) > stating a 20 BPF rate? I have read all the doc's on C54x, > bootloader, and any other referance I could find. the only thing I > have seen about that is the bootloader doc states a min 40 cpu > cycles between frames? I dont question if 20 bits per frame will > work, just that it is a fixed number compared to 40 cpu cycles which > could happen in two BCLKR's or some much less than 20BPF. > I hope to figure out what I have not understood. When I do I will > let the group know of my findings. Maybe someone else will be able > to make use some day of those findings. > > Caleb Austin |
(You need to be a member of c54x -- send a blank email to c54x-subscribe@yahoogroups.com )