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Discussion Groups | TMS320C54x | IFR
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
IFR - Micah Caudle - Sep 24 5:42:00 2003
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This statement from spru131g pg 6-27 about the IFR confuses me: "A 1 in any IFR bit indicates a pending interrupt. To clear an interrupt, write a 1 to the interrupt's corresponding bit in the IFR." It seems like if a 1 means an interrupt is pending, then you would write a 0 to clear it. How does writing a 1 to a bit that is already a 1 clear anything? I don't see how this could not confuse everyone who ever read it. Could anyone please clarify? Later on (pg 6-35) does mention clearing an IFR bit to 0. This only adds to my confusion! Thanks, Micah Caudle __________________________________ |
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Re: IFR - Tony Zampini - Sep 24 14:06:00 2003
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Micah, Writing a "1" to a particular IFR bit does indeed cause the bit to be cleared, thus, removing the pending interrupt. This is just the way the interrupt logic works. And there is a reason for this. If you think about it, if writing a "0" to an IFR bit caused a pending interrupt to clear, you could have a problem. If you wanted to clear just one pending interrupt, what value would you write to the IFR register? 1111....1110, or 0000...0000? The first value would clear the intended IFR bit, but set all the others causing false interrupts. The second value would clear ALL pending interrupts, even those that occurred AFTER you read the IFR register. Thus those interrupts would be lost. By doing it the way they did, all you need to do is read the IFR to determine what interrupts are pending, write that same value back to the IFR to clear ONLY THOSE BITS, and then process those interrupts. Now, any interrupts that arrive after the IFR is read, will be handled the next time the IFR is read, and will not be lost. Hope this helps. Tony ______________________________ Tony Zampini () Director of Engineering DSP Global 33 Plan Way, Bldg. #4 Warwick, RI 02886 Tel. 401-737-9900 FAX: 401-739-4197 www.dspglobal.com ----- Original Message ----- From: "Micah Caudle" <> To: "C54x Yahoo Groups" <> Sent: Wednesday, September 24, 2003 1:42 AM Subject: [c54x] IFR > This statement from spru131g pg 6-27 about the IFR > confuses me: > > "A 1 in any IFR bit indicates a pending interrupt. To > clear an interrupt, write a 1 to the interrupt's > corresponding bit in the IFR." > > It seems like if a 1 means an interrupt is pending, > then you would write a 0 to clear it. How does writing > a 1 to a bit that is already a 1 clear anything? I > don't see how this could not confuse everyone who ever > read it. Could anyone please clarify? Later on (pg > 6-35) does mention clearing an IFR bit to 0. This only > adds to my confusion! > > Thanks, > Micah Caudle > > __________________________________ > _____________________________________ |
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