Interrupt Servicing | TMS320C54x

Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).

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Hi all: I am using the '5410 eval board from Spectrum Digital and the TI emulator. I have a question about Interrupt Service Routines. I am using mnemonic assembly language only. The way I understand it, when the CPU receives an interrupt from the DMA, it jumps to the interrupt location (in my case 5ch), and reads the branch instruction at this location to get to the ISR. What is the best way to get the branch instruction into 5ch? Should I store the opcode to 5ch and the address I want it to go to in 5dh? Also, once I get the ISR written, how should I get it to reside at the program memory location that I want? For example, if I tell the CPU in the branch instruction that I want it to branch to at 1000h, how should I tell the compiler to put my ISR there? I have looked through the documentation, and have been unable to decipher what the best way to do this is. Any help would be greatly appreciated. Leigh Wells Electrical Engineer Acoustic Positioning Research

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Interrupt Servicing - Leigh Wells - Jul 8 16:04:00 1999