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Discussion Groups | TMS320C54x | TMS32VC5416:Issue in Interrupt Handling
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
TMS32VC5416:Issue in Interrupt Handling - WAISER MEHMOOD - Jan 25 7:35:48 2012
Hi,
I am working with TMS320VC5416, Code composer studio V3.3 and XDS510 usb
emulator.
I am working with external interrupt INT0, INT1, INT2. My code work fine on
simulator. On interrupt the cursor jumps to Interrupt Service routine and
execute successfully (Setting the interrupt by writing 1 on specific bit of
IFR from memory window).
When I switch to Emulator and trying to run same code. During loading I got
error "Data Verification failed at 0xFF80 Please verify target memory
map".
My Interrupt vector table is mapped on default location 0xFF80.
I am not using DSP/BIOS. Following files are used in my project.
main.c ----- main
vectors.asm ----- To handle interrupts
Here is my code, GEL and linker command file.
/********************Vectors.asm**************************/
.sect ".vectors"
.global _int0_handled,_int1_handled
.ref _ex_int00,_ex_int01,_ex_int02
;for reset & interrupt vectors
INT0: nop
nop
nop;nop
nop;nop
INT1: nop ;branch to interrupt vector 2
nop
nop;nop
nop;nop
INT2: nop
nop
nop
nop
INT3: nop
nop
nop
nop
INT4: nop
nop
nop
nop
INT5: nop
nop
nop
nop
INT6: nop
nop
nop
nop
INT7: nop
nop
nop
nop
INT8: nop
nop
nop
nop
INT9: nop
nop
nop
nop
INT10: nop
nop
nop
nop
INT11: nop
nop
nop
nop
INT12: nop
nop
nop
nop
INT13: nop
nop
nop
nop
INT14: nop
nop
nop
nop
INT15: nop
nop
nop
nop
INT16: b _ex_int00 ;branch to interrupt handler
_int0_handled: ret
nop
nop
INT17: b _ex_int01 ;branch to interrupt handler
_int1_handled: ret
nop
nop
INT18: b _ex_int02 ;branch to interrupt handler
_int2_handled: ret
nop
nop
/*********************************************/
/**************main.c*************************/
extern void int0_handled(void);
extern void int1_handled(void);
extern void int2_handled(void);
volatile unsigned int *IMR = (volatile unsigned int *) 0x0000;
volatile unsigned int *IFR = (volatile unsigned int *) 0x0001;
#define globalEnableInt() asm(" RSBX INTM ")
void ex_int00() //Interrupt Service Routine
{
globalEnableInt();
int0_handled();
}
void ex_int01() //Interrupt Service Routine
{
globalEnableInt();
int1_handled();
}
void ex_int02() //Interrupt Service Routine
{
globalEnableInt();
int2_handled();
}
void main(void)
{
unsigned short temp=0;
unsigned char counter=0;
*IMR= 0x07;
asm(" nop");
asm(" nop");
globalEnableInt();
asm(" nop");
while(1)
{
asm(" nop");
counter++;
}
}
/*********************************/
/***************Linker Command File***************/
-c
-l C:\CCStudio_v3.3\C5400\cgtools\lib\rts_ext.lib
MEMORY {
PAGE 0: /* program memory */
PROG_RAM : origin = 0x0080, length = 0x7F00
/* boot interrupt vector table location */
VECTORS : origin = 0xFF80, length = 0x80
PAGE 1:
DATA_RAM : origin = 0x8000, length = 0x8000
} /* MEMORY */
SECTIONS {
.text > PROG_RAM PAGE 0
.switch > PROG_RAM PAGE 0
.cinit > PROG_RAM PAGE 0
.vectors > VECTORS PAGE 0
.cio > DATA_RAM PAGE 1
.data > DATA_RAM PAGE 1
.bss > DATA_RAM PAGE 1
.const > DATA_RAM PAGE 1
.sysmem > DATA_RAM PAGE 1
.stack > DATA_RAM PAGE 1
.csldata > DATA_RAM PAGE 1
}
/********************GEL FILE***********************/
/*--------------------------------------------------------------*/
/* C5416_DSK.gel */
/* Version 3.00 */
/* */
/* This GEL file is designed to be used in conjunction with */
/* CCS 3.X and the TMS320VC5416 based DSK. */
/* */
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/* StartUp() */
/* This function is called each time CCS is started. */
/* Customize this function to perform desired initialization. */
/*--------------------------------------------------------------*/
StartUp()
{
setup_memory_map();
/*------------------------------------------------------*/
/* Uncomment the OnTargetConnect() call for CCS 2.X */
/* support. */
/* */
/* */
/*------------------------------------------------------*/
OnTargetConnect();
}
/*--------------------------------------------------------------*/
/* OnTargetConnect() */
/* This function is called by CCS when you do Debug->Connect on */
/* CCS 3.X. When using CCS 2.X, the OnTargetConnect() call */
/* should be uncommented from the StartUp() function. */
/*--------------------------------------------------------------*/
OnTargetConnect()
{
/*------------------------------------------------------*/
/* GEL_Reset() is used to deal with the worst case */
/* senario of unknown target state. If for some reason */
/* a reset is not desired upon target connection, */
/* GEL_Reset() may be removed and replaced with */
/* something "less brutal". */
/*------------------------------------------------------*/
GEL_Reset();
setup_extended_memory_map();
reset_cpu( );
GEL_TextOut("Gel StartUp Complete.\n");
}
/*--------------------------------------------------------------*/
/* setup_memory_map() */
/* Memory map setup */
/*--------------------------------------------------------------*/
setup_memory_map()
{
/* All memory maps are based on the PMST value of 0xFFE0 */
GEL_MapOn();
GEL_MapReset();
GEL_MapAdd( 0x00080u, 0, 0x07F80u, 1, 1 ); // DARAM
GEL_MapAdd( 0x08000u, 0, 0x0CFFFu, 1, 1 ); // External
GEL_MapAdd( 0x0C000u, 0, 0x03EFFu, 1, 1 ); //On -Chip ROM
GEL_MapAdd( 0x0FF80u, 0, 0x00080u, 1, 1 ); //On -Chip ROM
GEL_MapAdd( 0x00000u, 1, 0x00060u, 1, 1 ); // MMRs
GEL_MapAdd( 0x00060u, 1, 0x07FA0u, 1, 1 ); // DARAM
GEL_MapAdd( 0x08000u, 1, 0x08000u, 1, 1 ); // DARAM
GEL_MapAdd( 0x00000u, 2, 0x10000u, 1, 1 ); // IO Space
/*
GEL_MapAdd( 0x00080u, 0, 0x07F80u, 1, 1 ); // DARAM
GEL_MapAdd( 0x0Ff80u, 0, 0x0080u, 1, 1 ); // Vector
// GEL_MapAdd( 0x0F080u, 0, 0x00080u, 1, 1 ); // Remaining Vector Table
GEL_MapAdd( 0x08000u, 0, 0x08000u, 1, 1 ); // External
GEL_MapAdd( 0x00000u, 1, 0x00060u, 1, 1 ); // MMRs
GEL_MapAdd( 0x00060u, 1, 0x07FA0u, 1, 1 ); // DARAM
GEL_MapAdd( 0x08000u, 0, 0x08000u, 1, 1 ); // DARAM
GEL_MapAdd( 0x00000u, 2, 0x10000u, 1, 1 ); // IO Space*/
}
/*--------------------------------------------------------------*/
/* setup_extended_memory_map() */
/* Extended memory map setup */
/*--------------------------------------------------------------*/
setup_extended_memory_map()
{
/* Turn on the Extended Memory Map */
GEL_XMDef( 0x0000u, 0x01eu, 1, 0x8000u, 0x7f );
GEL_XMOn();
GEL_MapAdd( 0x18000u, 0, 0x08000u, 1, 1 ); // DARAM
GEL_MapAdd( 0x28000u, 0, 0x08000u, 1, 1 ); // SARAM
GEL_MapAdd( 0x38000u, 0, 0x08000u, 1, 1 ); // SARAM
}
/*--------------------------------------------------------------*/
/* clear_memory_map() */
/* Memory map disable */
/*--------------------------------------------------------------*/
clear_memory_map()
{
GEL_MapOff();
}
/*--------------------------------------------------------------*/
/* reset_cpu() */
/* Reset the CPU */
/*--------------------------------------------------------------*/
reset_cpu()
{
/* Set PMST to: OVLY on; DROM off, CLKOUT off */
#define PMST_VAL 0xFFa8u
/* Set wait-state control reg for: 2 wait states, 4 for I/O */
#define SWWSR_VAL 0x4492u
/* Set external-banks switch control for: set CONSEC and BH, CLKOUT/=2
*/
#define BSCR_VAL 0x0002u
PMST = PMST_VAL;
/*------------------------------------------------------*/
/* Don't change the wait states, let the application */
/* code handle it. */
/* Note: at power up all wait states will be the */
/* maximum (7) */
/* SWWSR = SWWSR_VAL; */
/*------------------------------------------------------*/
BSCR = BSCR_VAL;
disable_flash();
reset_peripherals();
GEL_TextOut("CPU Reset Complete.\n");
}
/*--------------------------------------------------------------*/
/* disable_flash() */
/* Disable Flash and Enable SRAM */
/*--------------------------------------------------------------*/
disable_flash()
{
/* Disable Flash so SRAM is visible */
*(int*)0x0005@io = 0x40;
GEL_TextOut("Flash is disabled.\n");
}
/*--------------------------------------------------------------*/
/* reset_peripherals() */
/* Peripheral Reset */
/*--------------------------------------------------------------*/
reset_peripherals()
{
IFR = 0xFFFFu;
IFR = 0x0000u;
reset_dma();
reset_mcbsp0();
reset_mcbsp1();
reset_mcbsp2();
reset_timer0();
reset_gpio();
}
/*--------------------------------------------------------------*/
/* reset_dma() */
/* DMA Reset */
/*--------------------------------------------------------------*/
reset_dma()
{
/* Set Peripheral Control Register Addresses for DEV_RESET */
#define DMPREC 0x0054u
#define DMSA 0x0055u
#define DMSDI 0x0056u
#define DMA_CH0_DMFSC_SUB_ADDR 0x0003u
#define DMA_CH1_DMFSC_SUB_ADDR 0x0008u
#define DMA_CH2_DMFSC_SUB_ADDR 0x000Du
#define DMA_CH3_DMFSC_SUB_ADDR 0x0012u
#define DMA_CH4_DMFSC_SUB_ADDR 0x0017u
#define DMA_CH5_DMFSC_SUB_ADDR 0x001cu
*(int *)DMPREC = 0;
*(int *)DMSA = DMA_CH0_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
*(int *)DMSA = DMA_CH1_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
*(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
*(int *)DMSA = DMA_CH3_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
*(int *)DMSA = DMA_CH4_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
*(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
*(int *)DMSDI = 0;
*(int *)DMSDI = 0;
}
/*--------------------------------------------------------------*/
/* reset_mcbsp0() */
/* MCBSP0 Reset */
/*--------------------------------------------------------------*/
reset_mcbsp0()
{
#define MCBSP0_SPSA 0x0038u
#define MCBSP0_SPSD 0x0039u
#define MCBSP_SPCR1_SUB_ADDR 0x0000u
#define MCBSP_SPCR2_SUB_ADDR 0x0001u
#define MCBSP_SRGR1_SUB_ADDR 0x0006u
#define MCBSP_SRGR2_SUB_ADDR 0x0007u
#define MCBSP_MCR1_SUB_ADDR 0x0008u
#define MCBSP_MCR2_SUB_ADDR 0x0009u
#define SRGR1_INIT 0x0001u
*(int *)MCBSP0_SPSA = MCBSP_SPCR1_SUB_ADDR;
*(int *)MCBSP0_SPSD = 0;
*(int *)MCBSP0_SPSA = MCBSP_SPCR2_SUB_ADDR;
*(int *)MCBSP0_SPSD = 0;
*(int *)MCBSP0_SPSA = MCBSP_SRGR1_SUB_ADDR;
*(int *)MCBSP0_SPSD = SRGR1_INIT;
*(int *)MCBSP0_SPSA = MCBSP_SRGR2_SUB_ADDR;
*(int *)MCBSP0_SPSD = 0;
*(int *)MCBSP0_SPSA = MCBSP_MCR1_SUB_ADDR;
*(int *)MCBSP0_SPSD = 0;
*(int *)MCBSP0_SPSA = MCBSP_MCR2_SUB_ADDR;
*(int *)MCBSP0_SPSD = 0;
}
/*--------------------------------------------------------------*/
/* reset_mcbsp1() */
/* MCBSP1 Reset */
/*--------------------------------------------------------------*/
reset_mcbsp1()
{
#define MCBSP1_SPSA 0x0048u
#define MCBSP1_SPSD 0x0049u
#define MCBSP_SPCR1_SUB_ADDR 0x0000u
#define MCBSP_SPCR2_SUB_ADDR 0x0001u
#define MCBSP_SRGR1_SUB_ADDR 0x0006u
#define MCBSP_SRGR2_SUB_ADDR 0x0007u
#define MCBSP_MCR1_SUB_ADDR 0x0008u
#define MCBSP_MCR2_SUB_ADDR 0x0009u
#define SRGR1_INIT 0x0001u
*(int *)MCBSP1_SPSA = MCBSP_SPCR1_SUB_ADDR;
*(int *)MCBSP1_SPSD = 0;
*(int *)MCBSP1_SPSA = MCBSP_SPCR2_SUB_ADDR;
*(int *)MCBSP1_SPSD = 0;
*(int *)MCBSP1_SPSA = MCBSP_SRGR1_SUB_ADDR;
*(int *)MCBSP1_SPSD = SRGR1_INIT;
*(int *)MCBSP1_SPSA = MCBSP_SRGR2_SUB_ADDR;
*(int *)MCBSP1_SPSD = 0;
*(int *)MCBSP1_SPSA = MCBSP_MCR1_SUB_ADDR;
*(int *)MCBSP1_SPSD = 0;
*(int *)MCBSP1_SPSA = MCBSP_MCR2_SUB_ADDR;
*(int *)MCBSP1_SPSD = 0;
}
/*--------------------------------------------------------------*/
/* reset_mcbsp2() */
/* MCBSP2 Reset */
/*--------------------------------------------------------------*/
reset_mcbsp2()
{
#define MCBSP2_SPSA 0x0034u
#define MCBSP2_SPSD 0x0035u
#define MCBSP_SPCR1_SUB_ADDR 0x0000u
#define MCBSP_SPCR2_SUB_ADDR 0x0001u
#define MCBSP_SRGR1_SUB_ADDR 0x0006u
#define MCBSP_SRGR2_SUB_ADDR 0x0007u
#define MCBSP_MCR1_SUB_ADDR 0x0008u
#define MCBSP_MCR2_SUB_ADDR 0x0009u
#define SRGR1_INIT 0x0001u
*(int *)MCBSP2_SPSA = MCBSP_SPCR1_SUB_ADDR;
*(int *)MCBSP2_SPSD = 0;
*(int *)MCBSP2_SPSA = MCBSP_SPCR2_SUB_ADDR;
*(int *)MCBSP2_SPSD = 0;
*(int *)MCBSP2_SPSA = MCBSP_SRGR1_SUB_ADDR;
*(int *)MCBSP2_SPSD = SRGR1_INIT;
*(int *)MCBSP2_SPSA = MCBSP_SRGR2_SUB_ADDR;
*(int *)MCBSP2_SPSD = 0;
*(int *)MCBSP2_SPSA = MCBSP_MCR1_SUB_ADDR;
*(int *)MCBSP2_SPSD = 0;
*(int *)MCBSP2_SPSA = MCBSP_MCR2_SUB_ADDR;
*(int *)MCBSP2_SPSD = 0;
}
/*--------------------------------------------------------------*/
/* reset_timer0() */
/* Timer0 Reset */
/*--------------------------------------------------------------*/
reset_timer0()
{
#define PRD0 0x0025u
#define TCR0 0x0026u
#define PRD1 0x0031u
#define TCR1 0x0032u
#define TIMER_STOP 0x0010u
#define TIMER_RESET 0x0020u
#define PRD_DEFAULT 0xFFFFu
*(int *)TCR0 = TIMER_STOP;
*(int *)PRD0 = PRD_DEFAULT;
*(int *)TCR0 = TIMER_RESET;
}
/*--------------------------------------------------------------*/
/* reset_gpio() */
/* GPIO Reset */
/*--------------------------------------------------------------*/
reset_gpio()
{
#define GPIOCR 0x0010u
*(int *)GPIOCR = 0;
}
/*--------------------------------------------------------------*/
/* DSK5416 MENU */
/*--------------------------------------------------------------*/
menuitem "DSK5416 Functions";
hotmenu Reset()
{
GEL_Reset();
reset_cpu( );
}
/*--------------------------------------------------------------*/
/* MEMORY MAP MENU */
/*--------------------------------------------------------------*/
menuitem "Memory Map";
hotmenu SetMemoryMap()
{
setup_memory_map();
}
hotmenu SetExtendedMemoryMap()
{
setup_extended_memory_map();
}
hotmenu ClearMemoryMap()
{
clear_memory_map();
}
##################################################################
I also map the interrupt vector table to 0x7F80 and modify the linker
command file for program ram and vector. I also changed the PMST to 0x7FA8.
This time code is loaded successfully. I run the code step by step, I did
not get interrupt in ISR but IFR reflect the activity on INT0, INT1, INT2.
I want to ask
1. Why code is not loaded on the 0xFF80 location?
2. If I move Interrupt vector table to 0x7f80 then why the interrupt not
occur?
Please let us know if there is any issue in GEL or linker command file or
code (main.c or vector.asm).
--
Regards
Waiser Mehmood
Design Engineer
C@RE Pvt. Ltd. <http://www.caerpvtltd.com>
______________________________Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.
(You need to be a member of c54x -- send a blank email to c54x-subscribe@yahoogroups.com )
Re: TMS32VC5416:Issue in Interrupt Handling - Jeff Brower - Jan 25 17:02:35 2012
Waiser-
> I am working with TMS320VC5416, Code composer studio V3.3 and XDS510 usb
> emulator.
>
> I am working with external interrupt INT0, INT1, INT2. My code work fine
on
> simulator. On interrupt the cursor jumps to Interrupt Service routine and
> execute successfully (Setting the interrupt by writing 1 on specific bit
of
> IFR from memory window).
>
> When I switch to Emulator and trying to run same code. During loading I
got
> error "Data Verification failed at 0xFF80 Please verify target memory
map".
>
> My Interrupt vector table is mapped on default location 0xFF80.
>
> I am not using DSP/BIOS. Following files are used in my project.
> main.c ----- main
> vectors.asm ----- To handle interrupts
>
> Here is my code, GEL and linker command file.
1) These statements in your .gel file appear to conflict:
GEL_MapAdd( 0x0FF80u, 0, 0x00080u, 1, 1 ); //On-Chip ROM
GEL_MapAdd( 0x0Ff80u, 0, 0x0080u, 1, 1 ); // Vector
Which one should apply? Maybe CCS is confused.
2) Depending on your MP/MC bit and IPTR settings, interrupt vectors may not be
mapped to 0xff80. IPTR is a field in
the PMST register. I noticed these lines in your .gel file:
#define PMST_VAL 0xFFa8u
/* All memory maps are based on the PMST value of 0xFFE0 */
which seems like another conflict. You have to study the C5416 data sheet, read
about IPTR, and be absolutely sure
that it matches where you locate vectors.
3) In most C54x applications I've seen, interrupt vectors normally start at
0x80. If the chip (bootloader), based on
IPTR value, thinks those are your vectors, then you're writing program data
where vectors should be.
Do you have a .gel file and some sample code for C54x, for example one of the
C54x DSK boards? I suggest you use that
for a reference.
-Jeff
> /********************Vectors.asm**************************/
> .sect ".vectors"
> .global _int0_handled,_int1_handled
> .ref _ex_int00,_ex_int01,_ex_int02
> ;for reset & interrupt vectors
>
> INT0: nop
> nop
> nop;nop
> nop;nop
>
> INT1: nop ;branch to interrupt vector 2
> nop
> nop;nop
> nop;nop
> INT2: nop
> nop
> nop
> nop
> INT3: nop
> nop
> nop
> nop
> INT4: nop
> nop
> nop
> nop
> INT5: nop
> nop
> nop
> nop
> INT6: nop
> nop
> nop
> nop
> INT7: nop
> nop
> nop
> nop
> INT8: nop
> nop
> nop
> nop
> INT9: nop
> nop
> nop
> nop
> INT10: nop
> nop
> nop
> nop
> INT11: nop
> nop
> nop
> nop
> INT12: nop
> nop
> nop
> nop
> INT13: nop
> nop
> nop
> nop
> INT14: nop
> nop
> nop
> nop
> INT15: nop
> nop
> nop
> nop
> INT16: b _ex_int00 ;branch to interrupt handler
> _int0_handled: ret
> nop
> nop
> INT17: b _ex_int01 ;branch to interrupt handler
> _int1_handled: ret
> nop
> nop
> INT18: b _ex_int02 ;branch to interrupt handler
> _int2_handled: ret
> nop
> nop
>
> /*********************************************/
> /**************main.c*************************/
> extern void int0_handled(void);
> extern void int1_handled(void);
> extern void int2_handled(void);
>
> volatile unsigned int *IMR = (volatile unsigned int *) 0x0000;
> volatile unsigned int *IFR = (volatile unsigned int *) 0x0001;
>
> #define globalEnableInt() asm(" RSBX INTM ")
>
> void ex_int00() //Interrupt Service Routine
> {
>
> globalEnableInt();
> int0_handled();
> }
> void ex_int01() //Interrupt Service Routine
> {
> globalEnableInt();
> int1_handled();
> }
>
> void ex_int02() //Interrupt Service Routine
> {
> globalEnableInt();
> int2_handled();
> }
>
> void main(void)
> {
>
> unsigned short temp=0;
> unsigned char counter=0;
>
> *IMR= 0x07;
> asm(" nop");
> asm(" nop");
>
> globalEnableInt();
>
> asm(" nop");
> while(1)
> {
> asm(" nop");
> counter++;
> }
>
> }
>
> /*********************************/
>
> /***************Linker Command File***************/
>
> -c
> -l C:\CCStudio_v3.3\C5400\cgtools\lib\rts_ext.lib
>
> MEMORY {
> PAGE 0: /* program memory */
>
> PROG_RAM : origin = 0x0080, length = 0x7F00
> /* boot interrupt vector table location */
>
> VECTORS : origin = 0xFF80, length = 0x80
>
> PAGE 1:
>
> DATA_RAM : origin = 0x8000, length = 0x8000
> } /* MEMORY */
> SECTIONS {
> .text > PROG_RAM PAGE 0
> .switch > PROG_RAM PAGE 0
> .cinit > PROG_RAM PAGE 0
> .vectors > VECTORS PAGE 0
>
> .cio > DATA_RAM PAGE 1
> .data > DATA_RAM PAGE 1
> .bss > DATA_RAM PAGE 1
> .const > DATA_RAM PAGE 1
> .sysmem > DATA_RAM PAGE 1
> .stack > DATA_RAM PAGE 1
> .csldata > DATA_RAM PAGE 1
> }
> /********************GEL FILE***********************/
> /*--------------------------------------------------------------*/
> /* C5416_DSK.gel */
> /* Version 3.00 */
> /* */
> /* This GEL file is designed to be used in conjunction with */
> /* CCS 3.X and the TMS320VC5416 based DSK. */
> /* */
> /*--------------------------------------------------------------*/
>
> /*--------------------------------------------------------------*/
> /* StartUp() */
> /* This function is called each time CCS is started. */
> /* Customize this function to perform desired initialization. */
> /*--------------------------------------------------------------*/
> StartUp()
> {
> setup_memory_map();
>
> /*------------------------------------------------------*/
> /* Uncomment the OnTargetConnect() call for CCS 2.X */
> /* support. */
> /* */
> /* */
> /*------------------------------------------------------*/
> OnTargetConnect();
> }
>
> /*--------------------------------------------------------------*/
> /* OnTargetConnect() */
> /* This function is called by CCS when you do Debug->Connect on */
> /* CCS 3.X. When using CCS 2.X, the OnTargetConnect() call */
> /* should be uncommented from the StartUp() function. */
> /*--------------------------------------------------------------*/
> OnTargetConnect()
> {
> /*------------------------------------------------------*/
> /* GEL_Reset() is used to deal with the worst case */
> /* senario of unknown target state. If for some reason */
> /* a reset is not desired upon target connection, */
> /* GEL_Reset() may be removed and replaced with */
> /* something "less brutal". */
> /*------------------------------------------------------*/
> GEL_Reset();
>
> setup_extended_memory_map();
>
> reset_cpu( );
>
> GEL_TextOut("Gel StartUp Complete.\n");
> }
>
> /*--------------------------------------------------------------*/
> /* setup_memory_map() */
> /* Memory map setup */
> /*--------------------------------------------------------------*/
> setup_memory_map()
> {
> /* All memory maps are based on the PMST value of 0xFFE0 */
> GEL_MapOn();
> GEL_MapReset();
>
> GEL_MapAdd( 0x00080u, 0, 0x07F80u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x08000u, 0, 0x0CFFFu, 1, 1 ); // External
> GEL_MapAdd( 0x0C000u, 0, 0x03EFFu, 1, 1 ); //On -Chip ROM
> GEL_MapAdd( 0x0FF80u, 0, 0x00080u, 1, 1 ); //On -Chip ROM
> GEL_MapAdd( 0x00000u, 1, 0x00060u, 1, 1 ); // MMRs
> GEL_MapAdd( 0x00060u, 1, 0x07FA0u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x08000u, 1, 0x08000u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x00000u, 2, 0x10000u, 1, 1 ); // IO Space
> /*
> GEL_MapAdd( 0x00080u, 0, 0x07F80u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x0Ff80u, 0, 0x0080u, 1, 1 ); // Vector
>
> // GEL_MapAdd( 0x0F080u, 0, 0x00080u, 1, 1 ); // Remaining Vector
Table
> GEL_MapAdd( 0x08000u, 0, 0x08000u, 1, 1 ); // External
> GEL_MapAdd( 0x00000u, 1, 0x00060u, 1, 1 ); // MMRs
> GEL_MapAdd( 0x00060u, 1, 0x07FA0u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x08000u, 0, 0x08000u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x00000u, 2, 0x10000u, 1, 1 ); // IO Space*/
> }
>
> /*--------------------------------------------------------------*/
> /* setup_extended_memory_map() */
> /* Extended memory map setup */
> /*--------------------------------------------------------------*/
> setup_extended_memory_map()
> {
> /* Turn on the Extended Memory Map */
> GEL_XMDef( 0x0000u, 0x01eu, 1, 0x8000u, 0x7f );
> GEL_XMOn();
>
> GEL_MapAdd( 0x18000u, 0, 0x08000u, 1, 1 ); // DARAM
> GEL_MapAdd( 0x28000u, 0, 0x08000u, 1, 1 ); // SARAM
> GEL_MapAdd( 0x38000u, 0, 0x08000u, 1, 1 ); // SARAM
> }
>
> /*--------------------------------------------------------------*/
> /* clear_memory_map() */
> /* Memory map disable */
> /*--------------------------------------------------------------*/
> clear_memory_map()
> {
> GEL_MapOff();
> }
>
> /*--------------------------------------------------------------*/
> /* reset_cpu() */
> /* Reset the CPU */
> /*--------------------------------------------------------------*/
> reset_cpu()
> {
> /* Set PMST to: OVLY on; DROM off, CLKOUT off */
> #define PMST_VAL 0xFFa8u
>
> /* Set wait-state control reg for: 2 wait states, 4 for I/O */
> #define SWWSR_VAL 0x4492u
>
> /* Set external-banks switch control for: set CONSEC and BH, CLKOUT/=2
> */
> #define BSCR_VAL 0x0002u
>
> PMST = PMST_VAL;
>
> /*------------------------------------------------------*/
> /* Don't change the wait states, let the application */
> /* code handle it. */
> /* Note: at power up all wait states will be the */
> /* maximum (7) */
> /* SWWSR = SWWSR_VAL; */
> /*------------------------------------------------------*/
>
> BSCR = BSCR_VAL;
>
> disable_flash();
>
> reset_peripherals();
>
> GEL_TextOut("CPU Reset Complete.\n");
> }
>
> /*--------------------------------------------------------------*/
> /* disable_flash() */
> /* Disable Flash and Enable SRAM */
> /*--------------------------------------------------------------*/
> disable_flash()
> {
> /* Disable Flash so SRAM is visible */
> *(int*)0x0005@io = 0x40;
>
> GEL_TextOut("Flash is disabled.\n");
> }
>
> /*--------------------------------------------------------------*/
> /* reset_peripherals() */
> /* Peripheral Reset */
> /*--------------------------------------------------------------*/
> reset_peripherals()
> {
> IFR = 0xFFFFu;
> IFR = 0x0000u;
>
> reset_dma();
> reset_mcbsp0();
> reset_mcbsp1();
> reset_mcbsp2();
> reset_timer0();
> reset_gpio();
> }
>
> /*--------------------------------------------------------------*/
> /* reset_dma() */
> /* DMA Reset */
> /*--------------------------------------------------------------*/
> reset_dma()
> {
> /* Set Peripheral Control Register Addresses for DEV_RESET */
> #define DMPREC 0x0054u
> #define DMSA 0x0055u
> #define DMSDI 0x0056u
>
> #define DMA_CH0_DMFSC_SUB_ADDR 0x0003u
> #define DMA_CH1_DMFSC_SUB_ADDR 0x0008u
> #define DMA_CH2_DMFSC_SUB_ADDR 0x000Du
> #define DMA_CH3_DMFSC_SUB_ADDR 0x0012u
> #define DMA_CH4_DMFSC_SUB_ADDR 0x0017u
> #define DMA_CH5_DMFSC_SUB_ADDR 0x001cu
>
> *(int *)DMPREC = 0;
>
> *(int *)DMSA = DMA_CH0_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> *(int *)DMSA = DMA_CH1_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> *(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> *(int *)DMSA = DMA_CH3_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> *(int *)DMSA = DMA_CH4_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> *(int *)DMSA = DMA_CH2_DMFSC_SUB_ADDR;
> *(int *)DMSDI = 0;
> *(int *)DMSDI = 0;
> }
>
> /*--------------------------------------------------------------*/
> /* reset_mcbsp0() */
> /* MCBSP0 Reset */
> /*--------------------------------------------------------------*/
> reset_mcbsp0()
> {
> #define MCBSP0_SPSA 0x0038u
> #define MCBSP0_SPSD 0x0039u
>
> #define MCBSP_SPCR1_SUB_ADDR 0x0000u
> #define MCBSP_SPCR2_SUB_ADDR 0x0001u
> #define MCBSP_SRGR1_SUB_ADDR 0x0006u
> #define MCBSP_SRGR2_SUB_ADDR 0x0007u
> #define MCBSP_MCR1_SUB_ADDR 0x0008u
> #define MCBSP_MCR2_SUB_ADDR 0x0009u
> #define SRGR1_INIT 0x0001u
>
> *(int *)MCBSP0_SPSA = MCBSP_SPCR1_SUB_ADDR;
> *(int *)MCBSP0_SPSD = 0;
> *(int *)MCBSP0_SPSA = MCBSP_SPCR2_SUB_ADDR;
> *(int *)MCBSP0_SPSD = 0;
>
> *(int *)MCBSP0_SPSA = MCBSP_SRGR1_SUB_ADDR;
> *(int *)MCBSP0_SPSD = SRGR1_INIT;
> *(int *)MCBSP0_SPSA = MCBSP_SRGR2_SUB_ADDR;
> *(int *)MCBSP0_SPSD = 0;
>
> *(int *)MCBSP0_SPSA = MCBSP_MCR1_SUB_ADDR;
> *(int *)MCBSP0_SPSD = 0;
> *(int *)MCBSP0_SPSA = MCBSP_MCR2_SUB_ADDR;
> *(int *)MCBSP0_SPSD = 0;
> }
>
> /*--------------------------------------------------------------*/
> /* reset_mcbsp1() */
> /* MCBSP1 Reset */
> /*--------------------------------------------------------------*/
> reset_mcbsp1()
> {
> #define MCBSP1_SPSA 0x0048u
> #define MCBSP1_SPSD 0x0049u
>
> #define MCBSP_SPCR1_SUB_ADDR 0x0000u
> #define MCBSP_SPCR2_SUB_ADDR 0x0001u
> #define MCBSP_SRGR1_SUB_ADDR 0x0006u
> #define MCBSP_SRGR2_SUB_ADDR 0x0007u
> #define MCBSP_MCR1_SUB_ADDR 0x0008u
> #define MCBSP_MCR2_SUB_ADDR 0x0009u
> #define SRGR1_INIT 0x0001u
>
> *(int *)MCBSP1_SPSA = MCBSP_SPCR1_SUB_ADDR;
> *(int *)MCBSP1_SPSD = 0;
> *(int *)MCBSP1_SPSA = MCBSP_SPCR2_SUB_ADDR;
> *(int *)MCBSP1_SPSD = 0;
>
> *(int *)MCBSP1_SPSA = MCBSP_SRGR1_SUB_ADDR;
> *(int *)MCBSP1_SPSD = SRGR1_INIT;
> *(int *)MCBSP1_SPSA = MCBSP_SRGR2_SUB_ADDR;
> *(int *)MCBSP1_SPSD = 0;
>
> *(int *)MCBSP1_SPSA = MCBSP_MCR1_SUB_ADDR;
> *(int *)MCBSP1_SPSD = 0;
> *(int *)MCBSP1_SPSA = MCBSP_MCR2_SUB_ADDR;
> *(int *)MCBSP1_SPSD = 0;
> }
>
> /*--------------------------------------------------------------*/
> /* reset_mcbsp2() */
> /* MCBSP2 Reset */
> /*--------------------------------------------------------------*/
> reset_mcbsp2()
> {
> #define MCBSP2_SPSA 0x0034u
> #define MCBSP2_SPSD 0x0035u
>
> #define MCBSP_SPCR1_SUB_ADDR 0x0000u
> #define MCBSP_SPCR2_SUB_ADDR 0x0001u
> #define MCBSP_SRGR1_SUB_ADDR 0x0006u
> #define MCBSP_SRGR2_SUB_ADDR 0x0007u
> #define MCBSP_MCR1_SUB_ADDR 0x0008u
> #define MCBSP_MCR2_SUB_ADDR 0x0009u
> #define SRGR1_INIT 0x0001u
>
> *(int *)MCBSP2_SPSA = MCBSP_SPCR1_SUB_ADDR;
> *(int *)MCBSP2_SPSD = 0;
> *(int *)MCBSP2_SPSA = MCBSP_SPCR2_SUB_ADDR;
> *(int *)MCBSP2_SPSD = 0;
>
> *(int *)MCBSP2_SPSA = MCBSP_SRGR1_SUB_ADDR;
> *(int *)MCBSP2_SPSD = SRGR1_INIT;
> *(int *)MCBSP2_SPSA = MCBSP_SRGR2_SUB_ADDR;
> *(int *)MCBSP2_SPSD = 0;
>
> *(int *)MCBSP2_SPSA = MCBSP_MCR1_SUB_ADDR;
> *(int *)MCBSP2_SPSD = 0;
> *(int *)MCBSP2_SPSA = MCBSP_MCR2_SUB_ADDR;
> *(int *)MCBSP2_SPSD = 0;
> }
>
> /*--------------------------------------------------------------*/
> /* reset_timer0() */
> /* Timer0 Reset */
> /*--------------------------------------------------------------*/
> reset_timer0()
> {
> #define PRD0 0x0025u
> #define TCR0 0x0026u
>
> #define PRD1 0x0031u
> #define TCR1 0x0032u
>
> #define TIMER_STOP 0x0010u
> #define TIMER_RESET 0x0020u
> #define PRD_DEFAULT 0xFFFFu
>
> *(int *)TCR0 = TIMER_STOP;
> *(int *)PRD0 = PRD_DEFAULT;
> *(int *)TCR0 = TIMER_RESET;
> }
>
> /*--------------------------------------------------------------*/
> /* reset_gpio() */
> /* GPIO Reset */
> /*--------------------------------------------------------------*/
> reset_gpio()
> {
> #define GPIOCR 0x0010u
>
> *(int *)GPIOCR = 0;
> }
>
> /*--------------------------------------------------------------*/
> /* DSK5416 MENU */
> /*--------------------------------------------------------------*/
> menuitem "DSK5416 Functions";
>
> hotmenu Reset()
> {
> GEL_Reset();
> reset_cpu( );
> }
>
> /*--------------------------------------------------------------*/
> /* MEMORY MAP MENU */
> /*--------------------------------------------------------------*/
> menuitem "Memory Map";
>
> hotmenu SetMemoryMap()
> {
> setup_memory_map();
> }
> hotmenu SetExtendedMemoryMap()
> {
> setup_extended_memory_map();
> }
> hotmenu ClearMemoryMap()
> {
> clear_memory_map();
> }
>
> ##################################################################
>
> I also map the interrupt vector table to 0x7F80 and modify the linker
> command file for program ram and vector. I also changed the PMST to
0x7FA8.
>
> This time code is loaded successfully. I run the code step by step, I did
> not get interrupt in ISR but IFR reflect the activity on INT0, INT1, INT2.
>
> I want to ask
>
> 1. Why code is not loaded on the 0xFF80 location?
> 2. If I move Interrupt vector table to 0x7f80 then why the interrupt not
> occur?
>
> Please let us know if there is any issue in GEL or linker command file or
> code (main.c or vector.asm).
>
> --
> Regards
> Waiser Mehmood
> Design Engineer
> C@RE Pvt. Ltd. <http://www.caerpvtltd.com
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