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Discussion Groups | TMS320C54x | C5402 DSK Interrupt Problem Fixed
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
C5402 DSK Interrupt Problem Fixed - Author Unknown - Nov 8 13:26:00 2001
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Got my interrupts going. I can now read data from the AD50 every time a receiver interrupt occurs. As Dave Helsley suggested, the problem I had was that the DRR register was being overrun because I was not reading it quick enough. If DRR has not been since the last RBR to DRR copy, a new word can not be transferred to DRR and hence, the receiver interrupt will not be cleared. I fixed this problem by doing a dummy read straight after enabling my global interrupts to clear out any data from DRR, and making sure in my ISR the data is read to clear DRR and hence clear the receiver ready interrupt. Also, stepping through my code would cause the AD50 to overrun anyway because by the time the code read DRR, it would already be overrun before I even stepped to the next instruction, ie. I can't step as fast as a DSP CPU ! So when testing AD50 run it continously. Thanks Dave Helsley for you help ! |
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RE: C5402 DSK Interrupt Problem Fixed - Dave Helsley - Nov 9 16:20:00 2001
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You're quite welcome -- I'm glad it worked out for you! :) This is a pretty good group, here ... it's nice to know I can contribute! Best regards, Dave Helsley -----Original Message----- From: [mailto:] Sent: Thursday, November 08, 2001 5:27 AM To: Subject: [c54x] C5402 DSK Interrupt Problem Fixed Got my interrupts going. I can now read data from the AD50 every time a receiver interrupt occurs. As Dave Helsley suggested, the problem I had was that the DRR register was being overrun because I was not reading it quick enough. If DRR has not been since the last RBR to DRR copy, a new word can not be transferred to DRR and hence, the receiver interrupt will not be cleared. I fixed this problem by doing a dummy read straight after enabling my global interrupts to clear out any data from DRR, and making sure in my ISR the data is read to clear DRR and hence clear the receiver ready interrupt. Also, stepping through my code would cause the AD50 to overrun anyway because by the time the code read DRR, it would already be overrun before I even stepped to the next instruction, ie. I can't step as fast as a DSP CPU ! So when testing AD50 run it continously. Thanks Dave Helsley for you help ! _____________________________________ |
New Code Sharing Section now Live on DSPRelated.com. Learn about the Reward Program for Contributors here.
(You need to be a member of c54x -- send a blank email to c54x-subscribe@yahoogroups.com )