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Discussion Groups | TMS320C54x | " ssbx intm" or "xc 1,unc" + "ssbx intm"?

Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).

  

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" ssbx intm" or "xc 1,unc" + "ssbx intm"? - Jane Shen - Feb 26 18:52:00 2002



Dear all,

Should we use the "xc 1,unc" + "ssbx intm" instead of mere "ssbx intm"
to avoid a potential pipeline bug?

For those of you who happened to have read the SPRA640. If you also read
the SPRA640A, you will notice that the author deletes the following
paragraphs in chapter 3.4:

"Wrong. If an interrupt occurs after line 1 is fetched, but before it is
executed, a problem occurs.
The CPU will automatically globally disable interrupts via the INTM bit,
and line 1, when it
executes, will have no effect. It will execute, since it had been
fetched before the interrupt
occurred. When the ISR completes, it will clear INTM, thus enabling
interrupts. Processing will
continue in our example at line 2, but interrupts will be enabled! So,
the original problem may
occur again. This will be another headache to debug, since the example
code clearly disables
interrupts. So, we need a way to protect the disabling instruction from
interruption. The solution
is as follows:
1 XC 1,UNC
2 SSBX INTM
3 STLM A,AR2
4 STLM B,AR2
5 NOP
6 LD *AR2,A
7 LD *AR2,B
8 RSBX INTM
Example 2B
The XC instruction on the C54x protects the next 1-word instruction from
interruption, e.g., it
ensures that the instruction will execute unconditionally."

I read the pipeline chapters of TI's CPU reference UG carefully. It
seems to me that the "ssbx intm" actually won't have a pipeline problem
as described in SPRA640. That might be the reason why the paragraphs
above are deleted. Am I right or I missed something?

I attached the SPRA640 for reference. The SPRA640A could be found at
http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?ab
stractName=spra640a.

Any reply will be appreciated.

Jane
Tri-Link Technologies Inc.
#301-8988, Fraserton Court
Burnaby, BC V5J 5H8
Tel: (604) 451-9113
Fax: (604) 451-9118
Email:


Attachment (not stored)
Programming and Debugging TIPs for DSP_BIOS_spra640.pdf
Type: application/octet-stream



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