Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
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I use the DMA channel 0 to send data to the DXR11 register ( transmit register McBsp1 ) and the DMA channel 1 to receive data from the DRR11 register (receive register McBsp1 ). The McBsp1 serial port is connected to a Texas ADC ( TLV 1570 ). The clock and frame sync is generated from the internal sample rate generator. The DMA element counter registers are set equal to the number of samples from the ADC. I check these registers to see when the sampling of the ADC is finished ( element counter=0 -> sampling finished ). It looks like the element counter registers start decrementing before I enable the DMA channel, receiver, transmitter and sample rate generator. I have also seen something similar on DMA channel 2. I use the DMA channel 2 to send data from the DSP to DXR10 register ( transmit register McBsp0 ). The McBsp0 is connected to a microcontroller, and the microcontroller generates the frame and clock signals. For example, if I want to send 8 bytes, I have to set the element counter register to 10. The correct value should have been one less than the number of bytes, 8-1=7. Here it also looks like the element counter start decrementing to early. The bytes send out on the serial port is correct, but the element counter has to be set equal to 10 to allow transmission of 8 bytes. This is very strange. I assume that the trigger event to the DMA should trigger both the element counter, the copying of data from source to destination and the post increment of the adress index. Have anyone else experienced anything similar to this problem ? Best regards Torgeir Jakobsen e-mail: |
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We found the problem ourselves. The serial port was disabled before all the bytes were send out. After the element counter is zero we have to wait before disabeling the transmitter. Best regards Torgeir Jakobsen e-mail: |