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Discussion Groups | TMS320C54x | TMS320C5409 EVM hold time problem
Technical discussions about the TI C54x DSPs (including the c5401, c5402, c5402a, c5404, c5407, c5409, c5409a, c5410, c5410a, c5416, c5420, c5421, c5441, c549, c5470 and c5471).
TMS320C5409 EVM hold time problem - Dozio - Mar 13 10:01:00 2002
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Hi, I'm developing a small Output port for the C5409 EVM. As output port I use a standard LVC273 and this is not a problem. But when I checked the timing (I/O PORT WRITE) I notice that the hold time of the DATA-BUS after a the STROBE (IOSTRB#) is only 2ns (worst case value at 100MHz clk). Is difficult to find a GATE (OR) that have only 2 ns delay time. So I looked the EVM schematics and I notice that on the board the use a standard GAL 5ns to generate the chip-selects of the external memories and I/O !!! At 100Mhz and at worst case it shouldn't work !!! Is the hold-time ( th(D)IOW )given by the datasheet (5409) wrong ? Thanks for your help Gian Carlo |
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