Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).
Hi all, I am trying to maximise throughput on a i2c link between a 55x chip and a 2806 chip. The 5507 is the master reciever and the 2806 is the slave transmitter. I am transferring 8 bytes in the following transfer (executed on the 5507 master): z = I2_read(datareceive,8,1,0x2,1,30000,1); The transfer happens successfully - On the scope, I see the start condition, first byte having the slave address and R/W =1, followed by 8 bytes of data. The master seems to be sending ACKs following the first 7 bytes and a NACK on following the 8th byte, which I believe is correct. The start condition, address byte and the first two data bytes are received in rapid succession without any delay between them. However, there is an inordinate delay between the clock bursts after data byte 3 through 8. Even after the 8th byte is received and the NACK is sent, there is a substantial delay before a stop condition is established. As a result of these delays, the total transfer takes 6 ms. Without the delays, it wouldn't take more than 600 microseconds. Given that the entire transmission takes place using the single read command above, how can I eliminate the gaps between the byte transmissions so that the enitre transfer occurs as a single burst of data/clocks? Thanks in advance Siva ______________________________ New Year Gift for Members of DSPRelated.com. Details here.
Hi, Anyone know which instruction to use to set SMXD to 1? Thanks, Hongyang ______________________________ New Year Gift for Members of DSPRelated.com. Details here.
Hi,
In algebraic, this is what it is.
bit(ST1, ST1_SXMD) = #1
You can find the details in the "help" in CCS.
Regards,
Shachi.
Hongyang Deng <d...@yahoo.com> wrote:
Hi,
Anyone know which instruction to use to set SMXD to 1?
Thanks, Hongyang
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