Hi Jeff,

5502 contains rev 2.x core for c55x. Hence you will see address wrap
around due to 16 bit addressing.

Regards,
Mihir

-----Original Message-----
From: Jeff Brower [mailto:j...@signalogic.com] 
Sent: Wednesday, August 02, 2006 5:13 AM
To: Mody, Mihir
Cc: c...@yahoogroups.com
Subject: [Fwd: RE: [c55x] malloc in different sections without DSP/BIOS]

Mihir-

We have a follow-up question about this.

Do you know if there is 3.x silicon for 5502?  If so, does the same
discussion below
apply?

In the 5502 chips we are using, the XAR reg does not increment past page
boundary.

Any advice appreciated, thanks.

-Jeff
-------- Original Message --------
Subject: RE: [c55x] malloc in different sections without DSP/BIOS
Date: Thu, 23 Sep 2004 18:31:14 +0530
From: "Mody, Mihir" <m...@ti.com>
To: "Lakshman" <l...@yahoo.com>,"piyush kaul"
<p...@yahoo.com>,
<C...@yahoogroups.com>

Hi Lakshman,

The revision 2.x of c55x CPU used 16 bit addressing, hence it will wrap
up to address
0 in same page when you increment at page boundary. The latest 3.0
revision of c55x
uses 23 bit addressing, hence it will move to next page. It is the way
hardware
designed and CPU behaves at page boundary. Let me stress that it is not
bug. There
won't be concept of patch (which is mostly valid for software) for this.
Hope this
clarifies behavior of revision 3. The compiler takes care for all C/C++
code. You
have careful of this fact only when you write code in assembly.

As far as I know, during allocation more then one page, you have
manually allocated
integer number of pages and remainder via malloc() or MEM_alloc()
functions.

Regards,
Mihir Mody,
Multimedia codecs group,
Texas Instruments India, Ltd,
Email : m...@ti.com
Phone : +91-80-25099307

-----Original Message-----
From: Lakshman [mailto:l...@yahoo.com]
Sent: Wednesday, September 22, 2004 8:20 PM
To: piyush kaul; C...@yahoogroups.com
Subject: Re: [c55x] malloc in different sections without DSP/BIOS
Hello All,

How to allocate more than one page(64Kb) memory on
C5510 and wht additional code must be added to prevent
pointer wrapping once it crosses a page boundry. 
I read TRM of C5510 silicon revision 3 where this bug
is fixed, Is there any patch available from TI for
fixing the above problem..

Thanks and regards
-Lakshman

--- piyush kaul <p...@yahoo.com> wrote:

> Hi Lakshman,
> 
> The "DARAM | SARAM" syntax is not going to allocate
> a
> heap in each DARAM and SARAM. The syntax just
> indicates to the linker to span a input section in
> two
> memory sections in case it doesn't fit into the
> first.
> You surely can't split the heap and choose which
> memory to use if you use the rts.lib malloc
> function.
> Since you don't want to use the BIOS, the only
> options
> left are, either to use static allocation, or
> implement a small heap manager of your own. For the
> former, you can use #DATA_SECTION pragmas to place
> the
> data in user defined sections and then choose to put
> them in either SARAM or DARAM. The latter is
> essentially equivalant to implementing some part of
> BIOS functionality on your own.
> 
> Hope it helps.
> 
> Regards
> Piyush
> 
> --- Lakshman <l...@yahoo.com> wrote:
> 
> > 
> > Hello All,
> > 
> > Can I malloc 40k memory of 5 buffers in C55x and
> how
> > will I allocate these buffers from different
> memory
> > sections Lets say one malloc operation in DARAM
> and
> > others in SDRAM. I tried doing malloc keeping
> > .sysmem
> > at DARAM | SDRAM in .cmd file but malloc fails to
> > allocate. One possible fix could be using
> MEM_alloc
> > where we can specify segment Id when using
> DSP/BIOS.
> > Since I'm not using DSP/BIOS in my project, I want
> > to
> > defer this idea....
> >  
> > Thanks and regards
> > -Lakshman