The following parallel instruction is executed incorrectly on C5509 
platform and executed correctly on C5510:

7dffff05_51d5      AND #65535,T1,AC0 || PSHBOTH XAR5

In C5509 XAR5 is NOT pushed to the stack at memory location pointed by 
XSP (stack pointer) ! Instead I have noticed that the content of XAR0 
(lower significant word) is the one that is pushed at the specified 
location in stack!! 

This instruction exists in MEM_alloc in DSP/BIOS for DSK5510 and C5509 
based platforms.

Mohammad-

> The following parallel instruction is executed incorrectly on C5509
> platform and executed correctly on C5510:
> 
> 7dffff05_51d5      AND #65535,T1,AC0 || PSHBOTH XAR5
> 
> In C5509 XAR5 is NOT pushed to the stack at memory location pointed by
> XSP (stack pointer) ! Instead I have noticed that the content of XAR0
> (lower significant word) is the one that is pushed at the specified
> location in stack!!
> 
> This instruction exists in MEM_alloc in DSP/BIOS for DSK5510 and C5509
> based platforms.

See advisory "CPU_16" in 5509 errata:

  http://focus.ti.com/lit/er/sprz006e/sprz006e.pdf

Also, note that in 5509A device this is fixed, and TI explicitly recommends to use
5509A instead of 5509.  You need to be using 5509A, why are you not?

To all young engineers:  *always check the errata first*.  TI has some of the best
errata you could ever ask for -- easily available, not under NDA, well documented. 
How you can possibly waste time checking for a bug that's already been clearly
documented by the chip vendor?  If I were your manager, you'd be in trouble :-) 
(Well not really, only if you made the error twice).

-Jeff

Mohammad-

> > See advisory "CPU_16" in 5509 errata:
> >
> >   http://focus.ti.com/lit/er/sprz006e/sprz006e.pdf
> >
> > Also, note that in 5509A device this is fixed, and TI explicitly
> recommends to use
> > 5509A instead of 5509.  You need to be using 5509A, why are you
> not?
> >
> > To all young engineers:  *always check the errata first*.  TI has
> some of the best
> > errata you could ever ask for -- easily available, not under NDA,
> well documented.
> > How you can possibly waste time checking for a bug that's already
> been clearly
> > documented by the chip vendor?  If I were your manager, you'd be
> in trouble :-)
> > (Well not really, only if you made the error twice).
> >
> > -Jeff
> > Actually we are working on DSP modules that use C5509

Who supplied the modules, a client?  If so, I hope your management was savvy enough
to charge more for work on 5509 than 5509A.  The client should have been given a
choice:  either pay more, or provide 5509A modules.

> Is there any workaround for this problem (other than changing the
> modules) and keep using DSP/BIOS APIs? (Is there a compiled version
> of DSP/BIOS that implements workarounds hinted by 5509 errata?)

My guess would be that 55x DSP/BIOS would avoid all errata, or at least there should
be a version that does, as TI wouldn't ship software that they knew had bugs for a
given chip.  Whether a separate 5509 version exists -- given so many 5509 errata --
is a good question for the TI hotline.

-Jeff