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Discussion Groups | TMS320C55x | DSK5510 McBSP as master/slave in SPI mode
Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).
DSK5510 McBSP as master/slave in SPI mode - mtrend123 - May 7 10:05:37 2007
I am a newbie to the DSk and to DSP programming in general.
I was wondering if it was possible to set up the McBsp 0 and 1 as a
master/slave to run a quick test?
I have been trying to do this with no success and wondering if I am
missing something.
Here is my configuration:
/* MCBSP_Config ConfigMaster - Master configuration*/
static MCBSP_Config ConfigMaster = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_RZF,
MCBSP_SPCR1_CLKSTP_NODELAY,
MCBSP_SPCR1_DXENA_OFF,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RSYNCERR_NO,
MCBSP_SPCR1_RRST_DISABLE
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_RESET,
MCBSP_SPCR2_GRST_RESET,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XRST_DISABLE
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(2),
MCBSP_RCR1_RWDLEN1_16BIT
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(2),
MCBSP_RCR2_RWDLEN2_16BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_1BIT
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(2),
MCBSP_XCR1_XWDLEN1_16BIT
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(2),
MCBSP_XCR2_XWDLEN2_16BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_1BIT
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0),
MCBSP_SRGR1_CLKGDV_OF(0x40)
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(0)
),
MCBSP_MCR1_RMK(
MCBSP_MCR1_RMCME_NO,
MCBSP_MCR1_RPBBLK_SF1,
MCBSP_MCR1_RPABLK_SF0,
MCBSP_MCR1_RCBLK_SF0,
MCBSP_MCR1_RMCM_CHENABLE
),
MCBSP_MCR2_RMK(
MCBSP_MCR2_XMCME_NO,
MCBSP_MCR2_XPBBLK_SF1,
MCBSP_MCR2_XPABLK_SF0,
MCBSP_MCR2_XCBLK_SF0,
MCBSP_MCR2_XMCM_ENNOMASK
),
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_ON,
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_INTERNAL,
// MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_FSRM_INTERNAL,
MCBSP_PCR_CLKXM_OUTPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_SCLKME_NO,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_RISING
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/* MCBSP_Config ConfigSlave - Slave configuration*/
static MCBSP_Config ConfigSlave = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_RZF,
MCBSP_SPCR1_CLKSTP_NODELAY,
MCBSP_SPCR1_DXENA_OFF,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RSYNCERR_NO,
MCBSP_SPCR1_RRST_DISABLE
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_RESET,
MCBSP_SPCR2_GRST_RESET,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XRST_DISABLE
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(2),
MCBSP_RCR1_RWDLEN1_16BIT
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(2),
MCBSP_RCR2_RWDLEN2_16BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(2),
MCBSP_XCR1_XWDLEN1_16BIT
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(2),
MCBSP_XCR2_XWDLEN2_16BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_0BIT
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0),
MCBSP_SRGR1_CLKGDV_OF(1)
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(0)
),
MCBSP_MCR1_RMK(
MCBSP_MCR1_RMCME_NO,
MCBSP_MCR1_RPBBLK_SF1,
MCBSP_MCR1_RPABLK_SF0,
MCBSP_MCR1_RCBLK_SF0,
MCBSP_MCR1_RMCM_CHENABLE
),
MCBSP_MCR2_RMK(
MCBSP_MCR2_XMCME_NO,
MCBSP_MCR2_XPBBLK_SF1,
MCBSP_MCR2_XPABLK_SF0,
MCBSP_MCR2_XCBLK_SF0,
MCBSP_MCR2_XMCM_ENNOMASK
),
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_ON,
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_EXTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_SCLKME_NO,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_RISING
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
I have jumpered the clkx fsx pins together and the DX0/DR1 DX1/DRO
together as well.
Basically I start the master, start the slave and write out "walking
ones" on the master. I then read them on the slave and write them
back out to the master.
Any suggestions?
thanks
m...@hotmail.com
(You need to be a member of c55x -- send a blank email to c55x-subscribe@yahoogroups.com )
Re: DSK5510 McBSP as master/slave in SPI mode - Jeff Brower - May 17 16:31:39 2007
M Trend-
> I am a newbie to the DSk and to DSP programming in general.
> I was wondering if it was possible to set up the McBsp 0 and 1 as a
> master/slave to run a quick test?
> I have been trying to do this with no success and wondering if I am
> missing something.
>
> I have jumpered the clkx fsx pins together and the DX0/DR1 DX1/DRO
> together as well.
> Basically I start the master, start the slave and write out "walking
> ones" on the master. I then read them on the slave and write them
> back out to the master.
Were you able to get this to work? Or still need some help? I'm guessing you might
have had some issue with configuring master to drive clock and framesync and slave to
receive (TI calls master "internal clock" and slave "external clock").
Another
gotcha is making sure master is sampling on falling edge and slave on rising edge.
-Jeff
> Here is my configuration:
> /* MCBSP_Config ConfigMaster - Master configuration*/
> static MCBSP_Config ConfigMaster = {
> MCBSP_SPCR1_RMK(
> MCBSP_SPCR1_DLB_OFF,
> MCBSP_SPCR1_RJUST_RZF,
> MCBSP_SPCR1_CLKSTP_NODELAY,
> MCBSP_SPCR1_DXENA_OFF,
> MCBSP_SPCR1_RINTM_RRDY,
> MCBSP_SPCR1_ABIS_DISABLE,
> MCBSP_SPCR1_RSYNCERR_NO,
> MCBSP_SPCR1_RRST_DISABLE
> ),
> MCBSP_SPCR2_RMK(
> MCBSP_SPCR2_FREE_YES,
> MCBSP_SPCR2_SOFT_NO,
> MCBSP_SPCR2_FRST_RESET,
> MCBSP_SPCR2_GRST_RESET,
> MCBSP_SPCR2_XINTM_XRDY,
> MCBSP_SPCR2_XSYNCERR_NO,
> MCBSP_SPCR2_XRST_DISABLE
> ),
> MCBSP_RCR1_RMK(
> MCBSP_RCR1_RFRLEN1_OF(2),
> MCBSP_RCR1_RWDLEN1_16BIT
> ),
> MCBSP_RCR2_RMK(
> MCBSP_RCR2_RPHASE_SINGLE,
> MCBSP_RCR2_RFRLEN2_OF(2),
> MCBSP_RCR2_RWDLEN2_16BIT,
> MCBSP_RCR2_RCOMPAND_MSB,
> MCBSP_RCR2_RFIG_YES,
> MCBSP_RCR2_RDATDLY_1BIT
> ),
> MCBSP_XCR1_RMK(
> MCBSP_XCR1_XFRLEN1_OF(2),
> MCBSP_XCR1_XWDLEN1_16BIT
> ),
> MCBSP_XCR2_RMK(
> MCBSP_XCR2_XPHASE_SINGLE,
> MCBSP_XCR2_XFRLEN2_OF(2),
> MCBSP_XCR2_XWDLEN2_16BIT,
> MCBSP_XCR2_XCOMPAND_MSB,
> MCBSP_XCR2_XFIG_YES,
> MCBSP_XCR2_XDATDLY_1BIT
> ),
> MCBSP_SRGR1_RMK(
> MCBSP_SRGR1_FWID_OF(0),
> MCBSP_SRGR1_CLKGDV_OF(0x40)
> ),
> MCBSP_SRGR2_RMK(
> MCBSP_SRGR2_GSYNC_FREE,
> MCBSP_SRGR2_CLKSP_RISING,
> MCBSP_SRGR2_CLKSM_INTERNAL,
> MCBSP_SRGR2_FSGM_DXR2XSR,
> MCBSP_SRGR2_FPER_OF(0)
> ),
> MCBSP_MCR1_RMK(
> MCBSP_MCR1_RMCME_NO,
> MCBSP_MCR1_RPBBLK_SF1,
> MCBSP_MCR1_RPABLK_SF0,
> MCBSP_MCR1_RCBLK_SF0,
> MCBSP_MCR1_RMCM_CHENABLE
> ),
> MCBSP_MCR2_RMK(
> MCBSP_MCR2_XMCME_NO,
> MCBSP_MCR2_XPBBLK_SF1,
> MCBSP_MCR2_XPABLK_SF0,
> MCBSP_MCR2_XCBLK_SF0,
> MCBSP_MCR2_XMCM_ENNOMASK
> ),
> MCBSP_PCR_RMK(
> MCBSP_PCR_IDLEEN_ON,
> MCBSP_PCR_XIOEN_SP,
> MCBSP_PCR_RIOEN_SP,
> MCBSP_PCR_FSXM_INTERNAL,
> // MCBSP_PCR_FSRM_EXTERNAL,
> MCBSP_PCR_FSRM_INTERNAL,
> MCBSP_PCR_CLKXM_OUTPUT,
> MCBSP_PCR_CLKRM_INPUT,
> MCBSP_PCR_SCLKME_NO,
> MCBSP_PCR_DXSTAT_0,
> MCBSP_PCR_FSXP_ACTIVELOW,
> MCBSP_PCR_FSRP_ACTIVEHIGH,
> MCBSP_PCR_CLKXP_RISING,
> MCBSP_PCR_CLKRP_RISING
> ),
> MCBSP_RCERA_DEFAULT,
> MCBSP_RCERB_DEFAULT,
> MCBSP_RCERC_DEFAULT,
> MCBSP_RCERD_DEFAULT,
> MCBSP_RCERE_DEFAULT,
> MCBSP_RCERF_DEFAULT,
> MCBSP_RCERG_DEFAULT,
> MCBSP_RCERH_DEFAULT,
> MCBSP_XCERA_DEFAULT,
> MCBSP_XCERB_DEFAULT,
> MCBSP_XCERC_DEFAULT,
> MCBSP_XCERD_DEFAULT,
> MCBSP_XCERE_DEFAULT,
> MCBSP_XCERF_DEFAULT,
> MCBSP_XCERG_DEFAULT,
> MCBSP_XCERH_DEFAULT
> };
>
> /* MCBSP_Config ConfigSlave - Slave configuration*/
> static MCBSP_Config ConfigSlave = {
> MCBSP_SPCR1_RMK(
> MCBSP_SPCR1_DLB_OFF,
> MCBSP_SPCR1_RJUST_RZF,
> MCBSP_SPCR1_CLKSTP_NODELAY,
> MCBSP_SPCR1_DXENA_OFF,
> MCBSP_SPCR1_RINTM_RRDY,
> MCBSP_SPCR1_ABIS_DISABLE,
> MCBSP_SPCR1_RSYNCERR_NO,
> MCBSP_SPCR1_RRST_DISABLE
> ),
> MCBSP_SPCR2_RMK(
> MCBSP_SPCR2_FREE_YES,
> MCBSP_SPCR2_SOFT_NO,
> MCBSP_SPCR2_FRST_RESET,
> MCBSP_SPCR2_GRST_RESET,
> MCBSP_SPCR2_XINTM_XRDY,
> MCBSP_SPCR2_XSYNCERR_NO,
> MCBSP_SPCR2_XRST_DISABLE
> ),
> MCBSP_RCR1_RMK(
> MCBSP_RCR1_RFRLEN1_OF(2),
> MCBSP_RCR1_RWDLEN1_16BIT
> ),
> MCBSP_RCR2_RMK(
> MCBSP_RCR2_RPHASE_SINGLE,
> MCBSP_RCR2_RFRLEN2_OF(2),
> MCBSP_RCR2_RWDLEN2_16BIT,
> MCBSP_RCR2_RCOMPAND_MSB,
> MCBSP_RCR2_RFIG_YES,
> MCBSP_RCR2_RDATDLY_0BIT
> ),
> MCBSP_XCR1_RMK(
> MCBSP_XCR1_XFRLEN1_OF(2),
> MCBSP_XCR1_XWDLEN1_16BIT
> ),
> MCBSP_XCR2_RMK(
> MCBSP_XCR2_XPHASE_SINGLE,
> MCBSP_XCR2_XFRLEN2_OF(2),
> MCBSP_XCR2_XWDLEN2_16BIT,
> MCBSP_XCR2_XCOMPAND_MSB,
> MCBSP_XCR2_XFIG_YES,
> MCBSP_XCR2_XDATDLY_0BIT
> ),
> MCBSP_SRGR1_RMK(
> MCBSP_SRGR1_FWID_OF(0),
> MCBSP_SRGR1_CLKGDV_OF(1)
> ),
> MCBSP_SRGR2_RMK(
> MCBSP_SRGR2_GSYNC_FREE,
> MCBSP_SRGR2_CLKSP_RISING,
> MCBSP_SRGR2_CLKSM_INTERNAL,
> MCBSP_SRGR2_FSGM_DXR2XSR,
> MCBSP_SRGR2_FPER_OF(0)
> ),
> MCBSP_MCR1_RMK(
> MCBSP_MCR1_RMCME_NO,
> MCBSP_MCR1_RPBBLK_SF1,
> MCBSP_MCR1_RPABLK_SF0,
> MCBSP_MCR1_RCBLK_SF0,
> MCBSP_MCR1_RMCM_CHENABLE
> ),
> MCBSP_MCR2_RMK(
> MCBSP_MCR2_XMCME_NO,
> MCBSP_MCR2_XPBBLK_SF1,
> MCBSP_MCR2_XPABLK_SF0,
> MCBSP_MCR2_XCBLK_SF0,
> MCBSP_MCR2_XMCM_ENNOMASK
> ),
> MCBSP_PCR_RMK(
> MCBSP_PCR_IDLEEN_ON,
> MCBSP_PCR_XIOEN_SP,
> MCBSP_PCR_RIOEN_SP,
> MCBSP_PCR_FSXM_EXTERNAL,
> MCBSP_PCR_FSRM_EXTERNAL,
> MCBSP_PCR_CLKXM_INPUT,
> MCBSP_PCR_CLKRM_INPUT,
> MCBSP_PCR_SCLKME_NO,
> MCBSP_PCR_DXSTAT_0,
> MCBSP_PCR_FSXP_ACTIVELOW,
> MCBSP_PCR_FSRP_ACTIVEHIGH,
> MCBSP_PCR_CLKXP_RISING,
> MCBSP_PCR_CLKRP_RISING
> ),
> MCBSP_RCERA_DEFAULT,
> MCBSP_RCERB_DEFAULT,
> MCBSP_RCERC_DEFAULT,
> MCBSP_RCERD_DEFAULT,
> MCBSP_RCERE_DEFAULT,
> MCBSP_RCERF_DEFAULT,
> MCBSP_RCERG_DEFAULT,
> MCBSP_RCERH_DEFAULT,
> MCBSP_XCERA_DEFAULT,
> MCBSP_XCERB_DEFAULT,
> MCBSP_XCERC_DEFAULT,
> MCBSP_XCERD_DEFAULT,
> MCBSP_XCERE_DEFAULT,
> MCBSP_XCERF_DEFAULT,
> MCBSP_XCERG_DEFAULT,
> MCBSP_XCERH_DEFAULT
> };
>
> I have jumpered the clkx fsx pins together and the DX0/DR1 DX1/DRO
> together as well.
> Basically I start the master, start the slave and write out "walking
> ones" on the master. I then read them on the slave and write them
> back out to the master.
>
> Any suggestions?
>
> thanks
> m...@hotmail.com
(You need to be a member of c55x -- send a blank email to c55x-subscribe@yahoogroups.com )