Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).
Hi, I have a questions about GPIO timing when I toggle them. It takes one cycle to change the pin high and one cycle to set it back to low. So when the DSP is clocked with 48 Mhz and I measure the pin with a logic analyzer I would expect to see a delta of about < 50ns. But what I measure is something > 200ns. Are there any explanations for this? Is the peripheral bus the reason?
Be. TEK- > I have a questions about GPIO timing when I toggle them. It takes one > cycle to change the pin high and one cycle to set it back to low. So > when the DSP is clocked with 48 Mhz and I measure the pin with a logic > analyzer I would expect to see a delta of about < 50ns. But what I > measure is something > 200ns. Are there any explanations for this? Is > the peripheral bus the reason? Enter into Google: bus stall site:dsprelated.com and read the first thread. -Jeff