Nils-
> thanks for the answer. So I guess the peripherial bus and its timing is the reason.
> Do you know of any manuals for the 5509 that state the number of extra cycles the
> bus tkes?
>

Not off hand.  My guess would be you could ask the TI hotline for a document.  They
tend to provide such "hands on measurement" docs, like EMIF throughput, if you can
demonstrate you need it and the info is not available online.
> I have another quick questions  that you could help me with. In the CSL DMA sample
> applications (dma2,dm3,dma4) that come with the generic 5509 examples there is
> always a second IRQ_SetVecs(0x10000) during the setup of the DMA channel. The first
> time it get setup to a vector address that is defined in an assembler file, but why
> would it have to be changed again.
> Thanks for your quick help
>

I'm not sure, as it doesn't look like any interrupts could occur between the two
calls to IRQ_setVecs().  What's the run-time value of &VECSTART?  Maybe you could
take out the first call and see if the code still runs.

-Jeff
> void main(void)
> {
>     /* Initialize CSL library - This is REQUIRED !!! */
>     CSL_init();
>
>     /* Set IVPD/IPVH to start of interrupt vector table */
>
>     IRQ_setVecs((Uint32)(&VECSTART));   // First init I understand :-)
>
>     /* Initialize source and destination buffers */
>     for (i = 0; i <= (N - 1); i++) {
>         dst1[i] = 0;
>         dst2[i] = 0;
>         src1[i] = i + 1;
>         src2[i] = (i + 1) * 2;
>     }
>
>     /* Call function to effect transfer */
>     taskFxn();
> }
>
> void taskFxn(void)
> {
> .....
>     DMA_config(myhDma, &myconfig);
>     /* Temporarily Disable All Interrupts */
>
>     old_intm = IRQ_globalDisable();
>     /* Clear any pending interrupts for DMA in IFR */
>
>     IRQ_clear(eventId);
>
>    /* Enable the DMA interrupt in IER register */
>
>     IRQ_enable(eventId);
>
>     /* Set Interrupt Vector Start Location */
>
>     IRQ_setVecs(0x10000);     // why ????
>
>     /* Place ISR address in associated vector location */
>
>     IRQ_plug(eventId, &dmaIsr);
>
>     /* Enable all maskable interrupts */
>
>     IRQ_globalEnable();
>
>     /* Enable DMA channel to begin transfer */
>
>     DMA_start(myhDma);
>
> ....
> }
> Nils Becker
>
> ----- Original Message ----
> From: Jeff Brower <j...@signalogic.com>
> To: b...@yahoo.com
> Cc: c...@yahoogroups.com
> Sent: Tuesday, May 8, 2007 5:08:47 PM
> Subject: Re: [c55x] GPIO on 5509a timing
>
> Be. TEK-
>
> > I have a questions about GPIO timing when I toggle them. It takes one
> > cycle to change the pin high and one cycle to set it back to low. So
> > when the DSP is clocked with 48 Mhz and I measure the pin with a logic
> > analyzer I would expect to see a delta of about < 50ns. But what I
> > measure is something > 200ns. Are there any explanations for this? Is
> > the peripheral bus the reason?
>
> Enter into Google:
>
> bus stall site:dsprelated. com
>
> and read the first thread.
>
> -Jeff
>