Altegoist-

> I use 5502 chip with 300 MHz clock frequency and configured PLLDIV3 so that
> SYSCLK3=150 MHz. It is far above allowed 100 MHz (SPRS166J, page 58,
> 3.10.4.4 External Memory Interface Clock Group) but everything seems to
> be ok. The chip write and read back MT48LC4M16A2 SDRAM (166 MHz Max Clock
> Frequency) properly. Have anyone tried to operate 5502 with 150MHz SDRAM
> clock? Can I rely on this result in serial production?

It's not uncommon for TI devices to run beyond their specs.  We've pushed many clock
rates and mem bus rates beyond the data sheet in the lab for test and measurement
purposes, or for prototype/demo purposes, but not for production.

Here is a TI paper by TI super-expert Gene Frantz that says "you can", but gives a
number of caveats:

  http://focus.ti.com/lit/ml/spry102/spry102.pdf

-Jeff