Hi all,

I am using the c5509 or c5510 DSP, and I'm trying to resolve the 
following problem.

My HW designer has created a circuit to generate a 20KHz clock, and 
my firmware has to create a 20KHz conversion start signal from the 
DSP that is synced to this clock (as per the figure below):

-----_____-----_____-----_____-----_____  20KHz Clock

_---------_---------_---------_---------  20KHz CONVST

I originally thought I could put the 20KHz signal onto the timer 
input (TIN) and then generate the CONVST output on TOUT. 
Unfortunately, I cannot do this as the TIN and TOUT functionality is 
mutually exclusive.

I then considered using 20KHz Clock on an external interrupt signal, 
and toggling a GPIO line (for CONVST) in the ISR for this interrupt. 
However, as there are other interrupts present and no means of 
prioritising them on the 5509/5510, I cannot guarantee that the 
CONVST will be synced to the Clock.

A further solution I considered was using 20KHz clock on TIN, and 
using TEVT to trigger a DMA transfer to CE3, and using the CE3 
signal as the CONVST. Again, this does not work, as in auto-reload 
mode, the timer period [(TDDR+1) x (PRD+1)] must be 4 cycles or 
greater, and I would need it to be 1 cycle as my input and required 
output are both 20KHz.

Does anyone have an idea how I might resolve this issue ?

Cheers,

Scotty

Scotty-

> I am using the c5509 or c5510 DSP, and I'm trying to resolve the
> following problem.
> 
> My HW designer has created a circuit to generate a 20KHz clock, and
> my firmware has to create a 20KHz conversion start signal from the
> DSP that is synced to this clock (as per the figure below):
> 
> -----_____-----_____-----_____-----_____  20KHz Clock
> 
> _---------_---------_---------_---------  20KHz CONVST
> 
> I originally thought I could put the 20KHz signal onto the timer
> input (TIN) and then generate the CONVST output on TOUT.
> Unfortunately, I cannot do this as the TIN and TOUT functionality is
> mutually exclusive.
> 
> I then considered using 20KHz Clock on an external interrupt signal,
> and toggling a GPIO line (for CONVST) in the ISR for this interrupt.
> However, as there are other interrupts present and no means of
> prioritising them on the 5509/5510, I cannot guarantee that the
> CONVST will be synced to the Clock.
> 
> A further solution I considered was using 20KHz clock on TIN, and
> using TEVT to trigger a DMA transfer to CE3, and using the CE3
> signal as the CONVST. Again, this does not work, as in auto-reload
> mode, the timer period [(TDDR+1) x (PRD+1)] must be 4 cycles or
> greater, and I would need it to be 1 cycle as my input and required
> output are both 20KHz.
> 
> Does anyone have an idea how I might resolve this issue ?

Yes, use the programmable logic that should be on your board -- FPGA, CPLD, etc.  All
you need is an inverted, somewhat reshaped version of the main clock.  The conversion
start signal should drive the ADC, and either a) the same or derived signal should
drive an ISR (or DMA read) on the DSP, or b) a "conversion done" signal from the ADC
should drive the ISR or DMA read.

-Jeff

--- In c...@yahoogroups.com, "smiffoz" <smiffoz@...> wrote:
>
> Hi all,
> 
> I am using the c5509 or c5510 DSP, and I'm trying to resolve the 
> following problem.
> 
> My HW designer has created a circuit to generate a 20KHz clock, and 
> my firmware has to create a 20KHz conversion start signal from the 
> DSP that is synced to this clock (as per the figure below):
> 
> -----_____-----_____-----_____-----_____  20KHz Clock
> 
> _---------_---------_---------_---------  20KHz CONVST
> 
> I originally thought I could put the 20KHz signal onto the timer 
> input (TIN) and then generate the CONVST output on TOUT. 
> Unfortunately, I cannot do this as the TIN and TOUT functionality 
is 
> mutually exclusive.
> 
> I then considered using 20KHz Clock on an external interrupt 
signal, 
> and toggling a GPIO line (for CONVST) in the ISR for this 
interrupt. 
> However, as there are other interrupts present and no means of 
> prioritising them on the 5509/5510, I cannot guarantee that the 
> CONVST will be synced to the Clock.
> 
> A further solution I considered was using 20KHz clock on TIN, and 
> using TEVT to trigger a DMA transfer to CE3, and using the CE3 
> signal as the CONVST. Again, this does not work, as in auto-reload 
> mode, the timer period [(TDDR+1) x (PRD+1)] must be 4 cycles or 
> greater, and I would need it to be 1 cycle as my input and required 
> output are both 20KHz.
> 
> Does anyone have an idea how I might resolve this issue ?
> 
> Cheers,
> 
> Scotty

Scotty,

Interrupt won't give a GPIO output of reliable frequency even if you 
were able to put it in the highest priority. Each time your interrupt 
has to preempt different number of layers of other ISRs.

DMA might work. Note that the cycles DMA requires are CPU cycles. 
Couldn't you tolerate several CPU cycles delay? That's only 0.01% of 
20KHz.

Or you can try McBsp. 20KHz inputs to CLKR, and set CLKX or FSX as 
slave to CLKR. But you have to find the register to reverse the phase 
or put appropriate delays, I guess it has least laterncy and it's 
doable.

Wei 
>