Hi,

I'm developing a TMS320C55x functional simulatior
through a tool  called ArchC, in order to get my B.Sc.
in Electrical Engineering. 

Right now, I have issues to identify user defined
parallel instructions ( || ). As far as I understand
it is at compile time when parallelism is determined
(implicit or explicit), so in the COFF file or the HEX
I should find the code that tells the DSP that the
following instructions must be executed in parallel,
but I found nothing. In the HEX there's one
instruction after another without any hint of
parallelism, maybe I'm looking 
at the wrong place? I need to find the code that tells
the DSP when to execute instructions in 
parallel in order to decode rightly the binary.

Please, I need some help.

Best regards,

Carl.

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi Tim,

Firts, thanks for your answer and your time.

Well, that's true. The parallel enable bit (E) is a
must but there are exceptions, for example,  Soft Dual
Parallelism. In that case these instructions don't
have an E bit, so: does the DSP check the validity of
the instructions and operands at runtime? Anyone
knows? Why the DSP should check what is already known
at compile time?

Sebastian.
--- Tim Thorpe <t...@romseydsp.com> escribió:

> Hello Carl,
> 
> I don't know the full answer to your question.
> However, from
> programming the C55x in assembler, I remember that
> for a user
> to parallel two instructions, at least one of them
> must possess
> a 'parallel enable bit'. Therefore, I would expect
> to find
> that of any pair of parallel instructions, one of
> them at
> least must assemble to a code different by one bit
> from the
> same instruction assembled on its own. Does this not
> happen
> in examples you've tried?
> 
> Tim.
> On Fri, 7 Mar 2008 18:56:39 +0100 (CET)
> bla bla <p...@yahoo.es> wrote:
> 
> > Hi,
> > 
> > I'm developing a TMS320C55x functional simulatior
> > through a tool  called ArchC, in order to get my
> B.Sc.
> > in Electrical Engineering. 
> > 
> > Right now, I have issues to identify user defined
> > parallel instructions ( || ). As far as I
> understand
> > it is at compile time when parallelism is
> determined
> > (implicit or explicit), so in the COFF file or the
> HEX
> > I should find the code that tells the DSP that the
> > following instructions must be executed in
> parallel,
> > but I found nothing. In the HEX there's one
> > instruction after another without any hint of
> > parallelism, maybe I'm looking 
> > at the wrong place? I need to find the code that
> tells
> > the DSP when to execute instructions in 
> > parallel in order to decode rightly the binary.
> > 
> > Please, I need some help.
> > 
> > Best regards,
> > 
> > Carl.
> > 
> > 
> -- 
>
------------------------------------------------------------
> Tim Thorpe	                        Tel: +44 1223
> 501569 
> t...@romseydsp.com                Fax: +44
> 1223 414402
>
------------------------------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

hi,


          If you look into c55x
instrunction opcode filed, on the MSB side there is some parellel enable bits, so setting these
bits may help .


pradeep.

--- On Fri, 7/3/08, bla bla
<p...@yahoo.es> wrote:
From: bla bla <p...@yahoo.es>
Subject: [c55x] Question: Where is the explicit parallel execution code in the binary?
To: c...@yahoogroups.com
Date: Friday, 7 March, 2008, 11:26 PM



    

            
Hi,



I'm developing a TMS320C55x functional simulatior

through a tool  called ArchC, in order to get my B.Sc.

in Electrical Engineering. 



Right now, I have issues to identify user defined

parallel instructions ( || ). As far as I understand

it is at compile time when parallelism is determined

(implicit or explicit), so in the COFF file or the HEX

I should find the code that tells the DSP that the

following instructions must be executed in parallel,

but I found nothing. In the HEX there's one

instruction after another without any hint of

parallelism, maybe I'm looking 

at the wrong place? I need to find the code that tells

the DSP when to execute instructions in 

parallel in order to decode rightly the binary.



Please, I need some help.



Best regards,



Carl.




    



      
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__,_._,___

hi, 

      dsp is not chekci=
ng for the validity of the instruction but compiler checks, dsp knows only =
to execute the instruction.  

      he=
y i don't much about compiler designs but I know something about dsp. =
 can u have database of instruction which all dsp supports and do a check ?=


       is this correct.

pradee=
p.

--- On Mon, 10/3/08, bla bla <p...@yahoo.es=
> wrote:
From: bla bla <perro_ver=
d...@yahoo.es>
Subject: Re: [c55x] Question: Where is the explici=
t parallel execution code in the binary?
To: t...@romseydsp.com, c=
5...@yahoogroups.com
Date: Monday, 10 March, 2008, 11:04 AM



    

            
Hi Tim,



Firts, thanks for your answer and your time.



Well, that's true. The parallel enable bit (E) is a

must but there are exceptions, for example,  Soft Dual

Parallelism. In that case these instructions don't

have an E bit, so: does the DSP check the validity of

the instructions and operands at runtime? Anyone

knows? Why the DSP should check what is already known

at compile time?



Sebastian.



--- Tim Thorpe <tim.thorpe@romseyds p.com> escribi=F3:



> Hello Carl,

> 

> I don't know the full answer to your question.

> However, from

> programming the C55x in assembler, I remember that

> for a user

> to parallel two instructions, at least one of them

> must possess

> a 'parallel enable bit'. Therefore, I would expect

> to find

> that of any pair of parallel instructions, one of

> them at

> least must assemble to a code different by one bit

> from the

> same instruction assembled on its own. Does this not

> happen

> in examples you've tried?

> 

> Tim.

> 

> 

> 

> 

> On Fri, 7 Mar 2008 18:56:39 +0100 (CET)

> bla bla <perro_verde_ lunar@yahoo. es> wrote:

> 

> > Hi,

> > 

> > I'm developing a TMS320C55x functional simulatior

> > through a tool  called ArchC, in order to get my

> B.Sc.

> > in Electrical Engineering. 

> > 

> > Right now, I have issues to identify user defined

> > parallel instructions ( || ). As far as I

> understand

> > it is at compile time when parallelism is

> determined

> > (implicit or explicit), so in the COFF file or the

> HEX

> > I should find the code that tells the DSP that the

> > following instructions must be executed in

> parallel,

> > but I found nothing. In the HEX there's one

> > instruction after another without any hint of

> > parallelism, maybe I'm looking 

> > at the wrong place? I need to find the code that

> tells

> > the DSP when to execute instructions in 

> > parallel in order to decode rightly the binary.

> > 

> > Please, I need some help.

> > 

> > Best regards,

> > 

> > Carl.

> > 

> > 

> 

> 

> -- 

>

------------ --------- --------- --------- --------- --------- -

> Tim Thorpe	                        Tel: +44 1223

> 501569 

> tim.thorpe@romseyds p.com                Fax: +44

> 1223 414402

>

------------ --------- --------- --------- --------- --------- -

> 

> 




    
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ed.com/groups/c55x/1.php



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__,_._,___

Read the Instruction Set Reference Guides for the 55x.
They explain all the available methods for parallelism, their rules,  
and their encodings.

--- In c...@yahoogroups.com, bla bla <perro_verde_lunar@...> wrote:
>
> Hi,
> 
> I'm developing a TMS320C55x functional simulatior
> through a tool  called ArchC, in order to get my B.Sc.
> in Electrical Engineering. 
> 
> Right now, I have issues to identify user defined
> parallel instructions ( || ). As far as I understand
> it is at compile time when parallelism is determined
> (implicit or explicit), so in the COFF file or the HEX
> I should find the code that tells the DSP that the
> following instructions must be executed in parallel,
> but I found nothing. In the HEX there's one
> instruction after another without any hint of
> parallelism, maybe I'm looking 
> at the wrong place? I need to find the code that tells
> the DSP when to execute instructions in 
> parallel in order to decode rightly the binary.
> 
> Please, I need some help.
> 
> Best regards,
> 
> Carl.
>

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi,

I've read the Instruction Set Reference Guide but my
problem it is not how to obtain paralleism on my DSP
code, my problem how to handle parallelism in the
simulator I am programming. I could program the rules
and let my simulator handle parallelism but losing too
many MIPS in the process.

Parallelism is determined at compile time in C55x, and
reading the CPU Reference Guide (SPRU371F), page 1-7,
it's clearly written that the instruction decoder
"determines whether the CPU has been INSTRUCTED to
execute two instructions in parallel", so I assume
that somewhere in the binary there are some hints for
the soft dual parallelism and other exceptions cases.
Maybe the DSP's decoder has a big hardware LUT that
automatically tells the DSP to execute the following
two instructions in parallel. 

Thanks for your answer and time.

Carl.
--- smee642003 <g...@quest-technologies.com>
escribió:

> Read the Instruction Set Reference Guides for the
> 55x.
> They explain all the available methods for
> parallelism, their rules,  
> and their encodings.
> 
> --- In c...@yahoogroups.com, bla bla
> <perro_verde_lunar@...> wrote:
> >
> > Hi,
> > 
> > I'm developing a TMS320C55x functional simulatior
> > through a tool  called ArchC, in order to get my
> B.Sc.
> > in Electrical Engineering. 
> > 
> > Right now, I have issues to identify user defined
> > parallel instructions ( || ). As far as I
> understand
> > it is at compile time when parallelism is
> determined
> > (implicit or explicit), so in the COFF file or the
> HEX
> > I should find the code that tells the DSP that the
> > following instructions must be executed in
> parallel,
> > but I found nothing. In the HEX there's one
> > instruction after another without any hint of
> > parallelism, maybe I'm looking 
> > at the wrong place? I need to find the code that
> tells
> > the DSP when to execute instructions in 
> > parallel in order to decode rightly the binary.
> > 
> > Please, I need some help.
> > 
> > Best regards,
> > 
> > Carl.
> 

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi Pradeep,

Regarding your first answer, I'm searching for hints
in the binary that help me to resolve the exceptions
to the Enable parallelism bit rule.

Regarding your second mail, I'm note quite sure what
are you telling me with this:

"hey i don't much about compiler designs but I know
something about dsp.  can u have database of
instruction which all dsp supports and do a check ?

       is this correct."

Are you asking me about the simulator? By database you
mean a decoder that support all of the instructions of
the DSP? In that case, yes. 

Thanks for your answer and time.

Carl. 
 
--- PRADEEP KUMAR <p...@yahoo.co.in> escribió:
---------------------------------
                  
hi, 

      dsp is not chekcing for the validity of the
instruction but compiler checks, dsp knows only to
execute the instruction.  

      hey i don't much about compiler designs but I
know something about dsp.  can u have database of
instruction which all dsp supports and do a check ?

       is this correct.

pradeep.

--- On Mon, 10/3/08, bla bla
<p...@yahoo.es> wrote:
From: bla bla <p...@yahoo.es>
Subject: Re: [c55x] Question: Where is the explicit
parallel execution code in the binary?
To: t...@romseydsp.com, c...@yahoogroups.com
Date: Monday, 10 March, 2008, 11:04 AM

Hi Tim,

Firts, thanks for your answer and your time.

Well, that's true. The parallel enable bit (E) is a
must but there are exceptions, for example,  Soft Dual
Parallelism. In that case these instructions don't
have an E bit, so: does the DSP check the validity of
the instructions and operands at runtime? Anyone
knows? Why the DSP should check what is already known
at compile time?

Sebastian.

--- Tim Thorpe <tim.thorpe@romseyds p.com> escribió:

> Hello Carl,
> 
> I don't know the full answer to your question.
> However, from
> programming the C55x in assembler, I remember that
> for a user
> to parallel two instructions, at least one of them
> must possess
> a 'parallel enable bit'. Therefore, I would expect
> to find
> that of any pair of parallel instructions, one of
> them at
> least must assemble to a code different by one bit
> from the
> same instruction assembled on its own. Does this not
> happen
> in examples you've tried?
> 
> Tim.
> On Fri, 7 Mar 2008 18:56:39 +0100 (CET)
> bla bla <perro_verde_ lunar@yahoo. es> wrote:
> 
> > Hi,
> > 
> > I'm developing a TMS320C55x functional simulatior
> > through a tool  called ArchC, in order to get my
> B.Sc.
> > in Electrical Engineering. 
> > 
> > Right now, I have issues to identify user defined
> > parallel instructions ( || ). As far as I
> understand
> > it is at compile time when parallelism is
> determined
> > (implicit or explicit), so in the COFF file or the
> HEX
> > I should find the code that tells the DSP that the
> > following instructions must be executed in
> parallel,
> > but I found nothing. In the HEX there's one
> > instruction after another without any hint of
> > parallelism, maybe I'm looking 
> > at the wrong place? I need to find the code that
> tells
> > the DSP when to execute instructions in 
> > parallel in order to decode rightly the binary.
> > 
> > Please, I need some help.
> > 
> > Best regards,
> > 
> > Carl.
> > 
> > 
> -- 
>
------------ --------- --------- --------- ---------
--------- -
> Tim Thorpe	                        Tel: +44 1223
> 501569 
> tim.thorpe@romseyds p.com                Fax: +44
> 1223 414402
>
------------ --------- --------- --------- ---------
--------- -
    
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Carl--
I have very little to offer in terms of answers for you but I will
offer this comment: your decision to expect for hints/explicit info
for ||ism in binary is justified and I will be highly surprised if the
DSP decoded that info any other way! Have you tried using edge
conditions like presence of RPTBLocal for outerloop and RPT for inner
loop to "guess" presence of ||ism around that edge?

This might be a good question for TI support rather than the group as
it has to do with TI tools than with DSP coding...But I dont know for
sure if TI support would respond to your request directly, so try
talking through your proff...

--Bhooshan

On Mon, Mar 10, 2008 at 10:07 PM, bla bla <p...@yahoo.es> wrot=
e:
> Hi,
>
> I've read the Instruction Set Reference Guide but my
> problem it is not how to obtain paralleism on my DSP
> code, my problem how to handle parallelism in the
> simulator I am programming. I could program the rules
> and let my simulator handle parallelism but losing too
> many MIPS in the process.
>
> Parallelism is determined at compile time in C55x, and
> reading the CPU Reference Guide (SPRU371F), page 1-7,
> it's clearly written that the instruction decoder
> "determines whether the CPU has been INSTRUCTED to
> execute two instructions in parallel", so I assume
> that somewhere in the binary there are some hints for
> the soft dual parallelism and other exceptions cases.
> Maybe the DSP's decoder has a big hardware LUT that
> automatically tells the DSP to execute the following
> two instructions in parallel.
>
> Thanks for your answer and time.
>
> Carl.
>
> --- smee642003 <g...@quest-technologies.com>
> escribi=F3:
>
> > Read the Instruction Set Reference Guides for the
> > 55x.
> > They explain all the available methods for
> > parallelism, their rules,
> > and their encodings.
> >
> > --- In c...@yahoogroups.com, bla bla
> > <perro_verde_lunar@...> wrote:
> > >
> > > Hi,
> > >
> > > I'm developing a TMS320C55x functional simulatior
> > > through a tool called ArchC, in order to get my
> > B.Sc.
> > > in Electrical Engineering.
> > >
> > > Right now, I have issues to identify user defined
> > > parallel instructions ( || ). As far as I
> > understand
> > > it is at compile time when parallelism is
> > determined
> > > (implicit or explicit), so in the COFF file or the
> > HEX
> > > I should find the code that tells the DSP that the
> > > following instructions must be executed in
> > parallel,
> > > but I found nothing. In the HEX there's one
> > > instruction after another without any hint of
> > > parallelism, maybe I'm looking
> > > at the wrong place? I need to find the code that
> > tells
> > > the DSP when to execute instructions in
> > > parallel in order to decode rightly the binary.
> > >
> > > Please, I need some help.
> > >
> > > Best regards,
> > >
> > > Carl.
> > >
> >
> >
> >
>=20

--=20
-------------------------------------------------------------------
"I've missed more than 9000 shots in my career.
I've lost almost 300 games. 26 times I've been trusted to take the
game winning shot and missed.
I've failed over and over again in my life.
And that is why I succeed."
 -- Michael Jordan
--------------------------------------------------------------------
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Tr=
anscoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm64=
67

=20

 hi,
yes I am asking you.

  &nb=
sp;     Regarding your latest mail, 

  =
;            I think=
, simulator won't execute the instruction in parallel. Its the illusion I t=
hink.


Upto my knowledge, Simulator mimics the dsp chip correct b=
ut it may not be able to execute the instrunction is parallel. Because on s=
imulator, some PC processor (AMD or Intel) is executing, not the DSP chip.<=
br>
           Hope my=
 answer is near to your expectation.

Pradeep.

   
--- On Mon, 10/3/08, bla bla <p...@yahoo.es>=
 wrote:
From: bla bla
 <p...@yahoo.es>
Subject: Re: [c55x] Question: Where =
is the explicit parallel execution code in the binary?
To: c55x@yahoogro=
ups.com
Date: Monday, 10 March, 2008, 11:04 PM



    

            
Hi Pradeep,



Regarding your first answer, I'm searching for hints

in the binary that help me to resolve the exceptions

to the Enable parallelism bit rule.



Regarding your second mail, I'm note quite sure what

are you telling me with this:



"hey i don't much about compiler designs but I know

something about dsp.  can u have database of

instruction which all dsp supports and do a check ?



is this correct."



Are you asking me about the simulator? By database you

mean a decoder that support all of the instructions of

the DSP? In that case, yes. 



Thanks for your answer and time.



Carl. 

 

--- PRADEEP KUMAR <p_kdl@yahoo. co.in> escribi=F3:



------------ --------- --------- ---

                  

hi, 



dsp is not chekcing for the validity of the

instruction but compiler checks, dsp knows only to

execute the instruction.  



hey i don't much about compiler designs but I

know something about dsp.  can u have database of

instruction which all dsp supports and do a check ?



is this correct.



pradeep.



--- On Mon, 10/3/08, bla bla

<perro_verde_ lunar@yahoo. es> wrote:

From: bla bla <perro_verde_ lunar@yahoo. es>

Subject: Re: [c55x] Question: Where is the explicit

parallel execution code in the binary?

To: tim.thorpe@romseyds p.com, c55x@yahoogroups. com

Date: Monday, 10 March, 2008, 11:04 AM



Hi Tim,



Firts, thanks for your answer and your time.



Well, that's true. The parallel enable bit (E) is a

must but there are exceptions, for example,  Soft Dual

Parallelism. In that case these instructions don't

have an E bit, so: does the DSP check the validity of

the instructions and operands at runtime? Anyone

knows? Why the DSP should check what is already known

at compile time?



Sebastian.



--- Tim Thorpe <tim.thorpe@ romseyds p.com> escribi=F3:



> Hello Carl,

> 

> I don't know the full answer to your question.

> However, from

> programming the C55x in assembler, I remember that

> for a user

> to parallel two instructions, at least one of them

> must possess

> a 'parallel enable bit'. Therefore, I would expect

> to find

> that of any pair of parallel instructions, one of

> them at

> least must assemble to a code different by one bit

> from the

> same instruction assembled on its own. Does this not

> happen

> in examples you've tried?

> 

> Tim.

> 

> 

> 

> 

> On Fri, 7 Mar 2008 18:56:39 +0100 (CET)

> bla bla <perro_verde_ lunar@yahoo. es> wrote:

> 

> > Hi,

> > 

> > I'm developing a TMS320C55x functional simulatior

> > through a tool  called ArchC, in order to get my

> B.Sc.

> > in Electrical Engineering. 

> > 

> > Right now, I have issues to identify user defined

> > parallel instructions ( || ). As far as I

> understand

> > it is at compile time when parallelism is

> determined

> > (implicit or explicit), so in the COFF file or the

> HEX

> > I should find the code that tells the DSP that the

> > following instructions must be executed in

> parallel,

> > but I found nothing. In the HEX there's one

> > instruction after another without any hint of

> > parallelism, maybe I'm looking 

> > at the wrong place? I need to find the code that

> tells

> > the DSP when to execute instructions in 

> > parallel in order to decode rightly the binary.

> > 

> > Please, I need some help.

> > 

> > Best regards,

> > 

> > Carl.

> > 

> > 

> 

> 

> -- 

>

------------ --------- --------- --------- ---------

--------- -

> Tim Thorpe	                        Tel: +44 1223

> 501569 

> tim.thorpe@romseyds p.com                Fax: +44

> 1223 414402

>

------------ --------- --------- --------- ---------

--------- -

> 

> 




    
=20=20
=20



      
 Unlimited freedom, unlimited storage. Get it now

__._,_.___







Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Tr=
anscoding Solution for Commercial & Consumer End Equipment: www.ti.com/=
dm6467



NEW!  You can now post a message or access and search the archives of =
this group on DSPRelated.com:

http://www.dsprelat=
ed.com/groups/c55x/1.php



_____________________________________

About this discussion group:



Archives:  htt=
p://www.dsprelated.com/groups/c55x/1.php



To Post:  Send an email to c...@yahoogroups.com



Other DSP Related Groups: =
http://www.dsprelated.com/groups.php














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br>



=20=20




      

      Your email settings: Individual Email|Traditional 

      Change settings via the Web (Ya=
hoo! ID required) 

      Change settings via email: Switch delivery to Daily Digest |=
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       Unsubscribe=20
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__,_._,___

I believe your assumptions are incorrect.  The whole point of "soft-
parallelism" is to do it at runtime, not compile-time.  This type of 
behavior is often seen in pipelined processors, especially those with 
multiple execution pipelines.

--- In c...@yahoogroups.com, bla bla <perro_verde_lunar@...> wrote:
>
> Hi,
> 
> I've read the Instruction Set Reference Guide but my
> problem it is not how to obtain paralleism on my DSP
> code, my problem how to handle parallelism in the
> simulator I am programming. I could program the rules
> and let my simulator handle parallelism but losing too
> many MIPS in the process.
> 
> Parallelism is determined at compile time in C55x, and
> reading the CPU Reference Guide (SPRU371F), page 1-7,
> it's clearly written that the instruction decoder
> "determines whether the CPU has been INSTRUCTED to
> execute two instructions in parallel", so I assume
> that somewhere in the binary there are some hints for
> the soft dual parallelism and other exceptions cases.
> Maybe the DSP's decoder has a big hardware LUT that
> automatically tells the DSP to execute the following
> two instructions in parallel. 
> 
> Thanks for your answer and time.
> 
> Carl.

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
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Hi Booshan,

I haven't tried to use edeg conditions but I will try,
thanks for the idea.
Regarding TI support I wrote a mail about 2 weeks ago
and guess, no response at all (bot automatic reply
doesn't count :P).

Thanks your answer and time.

Carl.

--- Bhooshan Iyer <b...@gmail.com> escribió:

> Carl--
> I have very little to offer in terms of answers for
> you but I will
> offer this comment: your decision to expect for
> hints/explicit info
> for ||ism in binary is justified and I will be
> highly surprised if the
> DSP decoded that info any other way! Have you tried
> using edge
> conditions like presence of RPTBLocal for outerloop
> and RPT for inner
> loop to "guess" presence of ||ism around that edge?
> 
> This might be a good question for TI support rather
> than the group as
> it has to do with TI tools than with DSP
> coding...But I dont know for
> sure if TI support would respond to your request
> directly, so try
> talking through your proff...
> 
> --Bhooshan
> 
> On Mon, Mar 10, 2008 at 10:07 PM, bla bla
> <p...@yahoo.es> wrote:
> >
> >
> >
> >
> > Hi,
> >
> > I've read the Instruction Set Reference Guide but
> my
> > problem it is not how to obtain paralleism on my
> DSP
> > code, my problem how to handle parallelism in the
> > simulator I am programming. I could program the
> rules
> > and let my simulator handle parallelism but losing
> too
> > many MIPS in the process.
> >
> > Parallelism is determined at compile time in C55x,
> and
> > reading the CPU Reference Guide (SPRU371F), page
> 1-7,
> > it's clearly written that the instruction decoder
> > "determines whether the CPU has been INSTRUCTED to
> > execute two instructions in parallel", so I assume
> > that somewhere in the binary there are some hints
> for
> > the soft dual parallelism and other exceptions
> cases.
> > Maybe the DSP's decoder has a big hardware LUT
> that
> > automatically tells the DSP to execute the
> following
> > two instructions in parallel.
> >
> > Thanks for your answer and time.
> >
> > Carl.
> >
> > --- smee642003 <g...@quest-technologies.com>
> > escribió:
> >
> >
> >
> > > Read the Instruction Set Reference Guides for
> the
> > > 55x.
> > > They explain all the available methods for
> > > parallelism, their rules,
> > > and their encodings.
> > >
> > > --- In c...@yahoogroups.com, bla bla
> > > <perro_verde_lunar@...> wrote:
> > > >
> > > > Hi,
> > > >
> > > > I'm developing a TMS320C55x functional
> simulatior
> > > > through a tool called ArchC, in order to get
> my
> > > B.Sc.
> > > > in Electrical Engineering.
> > > >
> > > > Right now, I have issues to identify user
> defined
> > > > parallel instructions ( || ). As far as I
> > > understand
> > > > it is at compile time when parallelism is
> > > determined
> > > > (implicit or explicit), so in the COFF file or
> the
> > > HEX
> > > > I should find the code that tells the DSP that
> the
> > > > following instructions must be executed in
> > > parallel,
> > > > but I found nothing. In the HEX there's one
> > > > instruction after another without any hint of
> > > > parallelism, maybe I'm looking
> > > > at the wrong place? I need to find the code
> that
> > > tells
> > > > the DSP when to execute instructions in
> > > > parallel in order to decode rightly the
> binary.
> > > >
> > > > Please, I need some help.
> > > >
> > > > Best regards,
> > > >
> > > > Carl.
> > > >
> > >
> > >
> > >
> >
> >
> 
------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi Pradeep,

The simulator executes the decoded instructions
serially, but it needs to know if a previous
instruction, like "repeat" will affect just the next
instruction or the next two paralleled instructions. I
need to know in advance when there's present
parallelism in order to preserve the behaviour of the
code.

It's different to execute:

RPT #3
MPYM *AR1-, *CDP, AC1 //Only MPYM is repeated 3 times
XOR AR2, T1

to:
RPT #3
MPYM *AR1-, *CDP, AC1 || XOR AR2, T1 //Both
instructions are repeated 3 times.

So what I need to find is how the compiler encodes (if
it does so) the parallel "operator" if neither of the
instructions have a parallel bit, but are legally
parallelizables. For example AADD TAx, TAy with AMOV
k8, TAz (see Soft Dual parallelism) 

Thanks for answer and time.

Carl.

--- PRADEEP KUMAR <p...@yahoo.co.in> escribió:
---------------------------------

 hi,
yes I am asking you.

        Regarding your latest mail, 

              I think, simulator won't execute the
instruction in parallel. Its the illusion I think.
Upto my knowledge, Simulator mimics the dsp chip
correct but it may not be able to execute the
instrunction is parallel. Because on simulator, some
PC processor (AMD or Intel) is executing, not the DSP
chip.

           Hope my answer is near to your expectation.

Pradeep.

--- On Mon, 10/3/08, bla bla
<p...@yahoo.es> wrote:
From: bla bla <p...@yahoo.es>
Subject: Re: [c55x] Question: Where is the explicit
parallel execution code in the binary?
To: c...@yahoogroups.com
Date: Monday, 10 March, 2008, 11:04 PM

Hi Pradeep,

Regarding your first answer, I'm searching for hints
in the binary that help me to resolve the exceptions
to the Enable parallelism bit rule.

Regarding your second mail, I'm note quite sure what
are you telling me with this:

"hey i don't much about compiler designs but I know
something about dsp.  can u have database of
instruction which all dsp supports and do a check ?

is this correct."

Are you asking me about the simulator? By database you
mean a decoder that support all of the instructions of
the DSP? In that case, yes. 

Thanks for your answer and time.

Carl. 
 
--- PRADEEP KUMAR <p_kdl@yahoo. co.in> escribió:

------------ --------- --------- ---
                  
hi, 

dsp is not chekcing for the validity of the
instruction but compiler checks, dsp knows only to
execute the instruction.  

hey i don't much about compiler designs but I
know something about dsp.  can u have database of
instruction which all dsp supports and do a check ?

is this correct.

pradeep.

--- On Mon, 10/3/08, bla bla
<perro_verde_ lunar@yahoo. es> wrote:
From: bla bla <perro_verde_ lunar@yahoo. es>
Subject: Re: [c55x] Question: Where is the explicit
parallel execution code in the binary?
To: tim.thorpe@romseyds p.com, c55x@yahoogroups. com
Date: Monday, 10 March, 2008, 11:04 AM

Hi Tim,

Firts, thanks for your answer and your time.

Well, that's true. The parallel enable bit (E) is a
must but there are exceptions, for example,  Soft Dual
Parallelism. In that case these instructions don't
have an E bit, so: does the DSP check the validity of
the instructions and operands at runtime? Anyone
knows? Why the DSP should check what is already known
at compile time?

Sebastian.

--- Tim Thorpe <tim.thorpe@ romseyds p.com> escribió:

> Hello Carl,
> 
> I don't know the full answer to your question.
> However, from
> programming the C55x in assembler, I remember that
> for a user
> to parallel two instructions, at least one of them
> must possess
> a 'parallel enable bit'. Therefore, I would expect
> to find
> that of any pair of parallel instructions, one of
> them at
> least must assemble to a code different by one bit
> from the
> same instruction assembled on its own. Does this not
> happen
> in examples you've tried?
> 
> Tim.
> On Fri, 7 Mar 2008 18:56:39 +0100 (CET)
> bla bla <perro_verde_ lunar@yahoo. es> wrote:
> 
> > Hi,
> > 
> > I'm developing a TMS320C55x functional simulatior
> > through a tool  called ArchC, in order to get my
> B.Sc.
> > in Electrical Engineering. 
> > 
> > Right now, I have issues to identify user defined
> > parallel instructions ( || ). As far as I
> understand
> > it is at compile time when parallelism is
> determined
> > (implicit or explicit), so in the COFF file or the
> HEX
> > I should find the code that tells the DSP that the
> > following instructions must be executed in
> parallel,
> > but I found nothing. In the HEX there's one
> > instruction after another without any hint of
> > parallelism, maybe I'm looking 
> > at the wrong place? I need to find the code that
> tells
> > the DSP when to execute instructions in 
> > parallel in order to decode rightly the binary.
> > 
> > Please, I need some help.
> > 
> > Best regards,
> > 
> > Carl.
> > 
> > 
> -- 
>
------------ --------- --------- --------- ---------
--------- -
> Tim Thorpe	                        Tel: +44 1223
> 501569 
> tim.thorpe@romseyds p.com                Fax: +44
> 1223 414402
>
------------ --------- --------- --------- ---------
--------- -

------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi,

Maybe you are right but as old as it is the c55x, it
would have cost a serious amount of power and area to
implement such a stratetegy for hardware designed to
be power efficient and for mobile devices. 

But I'm preparing for the worst case: no hint at all.

Thanks for your answer and time.

Carl.

--- smee642003 <g...@quest-technologies.com>
escribió:

> I believe your assumptions are incorrect.  The whole
> point of "soft-
> parallelism" is to do it at runtime, not
> compile-time.  This type of 
> behavior is often seen in pipelined processors,
> especially those with 
> multiple execution pipelines.
> 
> --- In c...@yahoogroups.com, bla bla
> <perro_verde_lunar@...> wrote:
> >
> > Hi,
> > 
> > I've read the Instruction Set Reference Guide but
> my
> > problem it is not how to obtain paralleism on my
> DSP
> > code, my problem how to handle parallelism in the
> > simulator I am programming. I could program the
> rules
> > and let my simulator handle parallelism but losing
> too
> > many MIPS in the process.
> > 
> > Parallelism is determined at compile time in C55x,
> and
> > reading the CPU Reference Guide (SPRU371F), page
> 1-7,
> > it's clearly written that the instruction decoder
> > "determines whether the CPU has been INSTRUCTED to
> > execute two instructions in parallel", so I assume
> > that somewhere in the binary there are some hints
> for
> > the soft dual parallelism and other exceptions
> cases.
> > Maybe the DSP's decoder has a big hardware LUT
> that
> > automatically tells the DSP to execute the
> following
> > two instructions in parallel. 
> > 
> > Thanks for your answer and time.
> > 
> > Carl.
> 

------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467