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Discussion Groups | TMS320C55x | Rev 2.1 Silicon

Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).

  

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Rev 2.1 Silicon - smartyump - Jun 19 20:46:00 2002

I am looking for rev 2.1 c5510. Does anyone know where to get it?

Thanks



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Re: Rev 2.1 Silicon - Arius - Rick Collins - Jun 20 13:56:00 2002

At 04:46 PM 6/19/02, smartyump wrote:
>I am looking for rev 2.1 c5510. Does anyone know where to get it?
>
>Thanks

I contacted TI support in May and this is what I was told.

"""""""""""""&q uot;
The TMS320VC5510 is not yet available for production. The device is
currently in rev2.0 TMX silicon. A revision 2.1 is scheduled for late this
quarter, however, I don't have any firm dates on its release as of yet. The
device currently is scheduled to be fully qualified for production sometime
in late 3Q02 or early 4Q02, but again, I don't have any dates to provide at
this time.
"""""""""""""&q uot;

You might try them again and see if they have any more accurate dates. Rick Collins
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX



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Possible Bug in CCS-2.1 assembler??? - Gaurav - Jun 21 15:12:00 2002

Hi,
I am using CCS ver 2.1 and faced some problem on using algebraic version
of assembly instruction for BTST.

Mnemonic instruction "BTST AR6,AC0,TC1" compiles successfully.

Algebraic equivalent of the above instruction "TC1 = bit (AC0,AR6)" gives
compilation error (parse ERROR).
"test.asm", ERROR! at line 9: [E0000] parse error
TC1 = bit(AC0,AR6)
^

However, the instruction "TC1 = bit (AC0,@#12)" works.
Infact no Bit operation on registers is working in Algerbric form.
I tried the similar thing in CCS ver 2.0 also and the result was same.
Has anyone faced a similar problem??

Thanks in advance

With Regards,
Gaurav


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