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Hi all, I am facing a problem with the following piece of code.on evm 5510 MOV AR3,AR2 MOV AR3,AR1 ADD T0 ,AR2 ; T0 HAS SOME NON ZERO VALUE RPTSUB CSR, #1 MACM *AR1+,*AR2+,AC0 AR3 points to location 7000h. and csr is loaded with 255. now the problem is in the MAC instruction. In the 55x simulator ittaks 256 cycles and so on to execute but in 5510 simulator and 5510 EVM ti takes double of it (ie MAC taking 512 cycles) . Why is it so .. where is this pipeline stall happening.As an experiment AR2 and AR1 were set pointing to diff memory banks. but problem persisted. Any solution to it. Thanks Amit Jain Engineer, Ittiam Systems (P) Ltd. Consulate 1, 1 Richmond Road, Bangalore 560025, India. T +91 80 2237660, +91 80 2237760 Ext. 1050 F +91 80 2237905 , DISCLAIMER: The information contained in this communication is intended solely for the use of the individual or entity to whom it is addressed and others authorized to receive it. It may contain confidential or legally privileged information of Ittiam Systems Private Limited. If you are not the intended recipient you are hereby notified that any disclosure, copying, distribution or taking any action in reliance on the contents of this information is strictly prohibited and may be unlawful. If you have received this communication in error, please notify us immediately by responding to the sender of this e-mail and/or Administrator <mailto:> and then delete it from your system. E-mail transmission is not guaranteed to be secure or error-free as information can be intercepted, corrupted, lost, destroyed, delayed, incomplete, or contain viruses. Ittiam Systems Private Limited <http://www.ittiam.com/> is therefore neither liable for the proper and complete transmission of the information contained in this communication nor for any delay in its receipt. ------------------

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"Amit Jain" <> wrote: > I am facing a problem with the following piece of code.on evm 5510 > MOV AR3,AR2 > MOV AR3,AR1 > ADD T0 ,AR2 ; T0 HAS SOME NON ZERO VALUE > RPTSUB CSR, #1 > MACM *AR1+,*AR2+,AC0 >AR3 points to location 7000h. and csr is loaded with 255. now the >problem is in the MAC instruction. In the 55x simulator ittaks 256 >cycles and so on to execute >but in 5510 simulator and 5510 EVM ti takes double of it (ie MAC taking >512 cycles) . Why is it so .. where is this pipeline stall happening.As >an experiment AR2 and AR1 >were set pointing to diff memory banks. but problem persisted. Any >solution to it. As I think you already realize, there should be no stall and it shouldn't matter where the operands go (so long as they are in DARAM if on the same block). I've been seeing similar problems with both c55x simulator and c5510 simulator: it applies to other instructions than just the MAC above, and happens irrespective of whether you use localrepeat or single repeat instructions. When I do a loop of 100 MACS or dual MACS on the 5510 simulator, I can get cycle counts of 200 or 230 according to how many operands and where they are. On the 55x simulator, I can get 100 or 130. In neither case does the dual MAC respond correctly to whether the operands are on the same or different blocks. I've been holding off from getting hardware until it seems that the majority of silicon bugs have gone, but was just wondering whether to get a prototype board in order to get correct cycle counts for my code. If you are seeing something similar on hardware, that's even more perplexing. As for the simulator, doesn't it come from Bangalore? Can't you just take a taxi across town, knock on their door and ask them what they're playing at? Tim. ------------------------------------------------------------ Tim Thorpe Tel: +44 1223 240366 Fax: +44 1223 414402 ------------------------------------------------------------

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Start your Android Ice Cream Sandwich development on TI's AM35x Sitara ARM Cortex-A8 processor today.



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