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Discussion Groups | TMS320C55x | Problem with a McBSP connected to a I2S master

Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).

  

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Problem with a McBSP connected to a I2S master - peejayblack - Jan 17 21:34:00 2005





Hello,
I've been having difficulty with a McBSP interface. It's
connected to a
I2S A-D converter set up as a master. I.e. it generates the bit clock
and frame sync. I'm receiving only so the A-D just pumps the clock
out.

I can get the receive to fire an interrupt, but all I read out of the
DRR's is zero.
I do have the proper signals clocking in ( Viewed on a scope ) The
inputs seem ok as I reprogrammed the receive lines as input ports and
I'm able to read them. I read the DRR's in the proper
sequence 2 then 1.

Since the A-D converter is generating all the clocks I really
don't
need to be to very concerned about the clock generator …or do
I??? My
assumption is based on SPRA595. Its for the c6000 but the McBSP are
very similar.

Any Ideas ?
peejayblack





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Re: Problem with a McBSP connected to a I2S master - Harland Christofferson - Jan 18 10:49:00 2005


can you furnish mcbsp register configuration info?

At Tuesday, 18 January 2005, "peejayblack" <>
wrote:

>Hello,
>I've been having difficulty with a McBSP interface. It's
>connected to a
>I2S A-D converter set up as a master. I.e. it generates the bit clock
>and frame sync. I'm receiving only so the A-D just pumps the clock
>out.
>
>I can get the receive to fire an interrupt, but all I read out of the
>DRR's is zero.
>I do have the proper signals clocking in ( Viewed on a scope ) The
>inputs seem ok as I reprogrammed the receive lines as input ports and
>I'm able to read them. I read the DRR's in the proper
>sequence 2 then 1.
>
>Since the A-D converter is generating all the clocks I really
>don't
>need to be to very concerned about the clock generator …or do
>I??? My
>assumption is based on SPRA595. Its for the c6000 but the McBSP are
>very similar.
>
>Any Ideas ?
>peejayblack
>
----------------------------------------------------------------------
Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems

http://www.zerocrossings.com/



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Re: Problem with a McBSP connected to a I2S master - peejayblack - Jan 18 11:26:00 2005

Thanks for the reply

I was using the CSL. I have since converted the McBSP setup to my own
SOP McBSP setup template... With the same result. If you copy the code
below into an editor it should clean up.

Do the DRR's zero if there is a frame error?

Thanks
PeeJayBlack
====================================================================
====================================================================

//===========================================================================
//= Initialization constants for mcbsp0
//===========================================================================
SPCR1
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 DLB -- RJUST -- CLKSTP1 |
0 0 0 0
//- |+--- 0 CLKSTP0 xx xx xx |
0 0 0 0
//- ||+-- 0 DXENA xx -- RINTM -- |
0 0 0 0
//- |||+- 0 RSYNCERR RFULL RRDY ~RRST |
0 0 0 0
//- ||||
#define BSP0_SPCR1 0x0000
#define RRST_ENAB 0x0001

//===========================================================================
SPCR2
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 xx xx xx xx |
0 0 0 0
//- |+--- 2 xx xx FREE SOFT |
0 0 1 1
//- ||+-- 0 ~FRST ~GRST -- XINTM -- |
0 0 0 0
//- |||+- 0 XSYNCERR ~XEMPTY XRDY ~XRST |
0 0 0 0
//- ||||
#define BSP0_SPCR2 0x0300

//==============================================================================
RCR1
// | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 xx RFRLEN1-6 ------ RFRLEN1-4 |
0 0 0 0
//- |+--- 0 RFRLEN1-3 --------------- RFRLEN1-0 |
0 0 0 0
//- ||+-- 4 RWDLEN1-2 ----- RWDLEN1-0 xx |
1 0 1 0
//- |||+- 0 xx xx xx xx |
0 0 0 0
//- ||||
#define BSP0_RCR1 0x01a0 //===========================================================================
RCR2
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 RPHASE RFRLEN2-6 ------- RFRLEN2-4 |
1 0 0 0
//- |+--- 0 RFRLEN2-3 --------------- RFRLEN2-0 |
0 0 0 0
//- ||+-- 0 RWDLEN2 -------- RWDLEN2 RCOMPAND |
1 0 1 0
//- |||+- 1 RCOMPAND RFIG -- RDATDLY -- |
0 1 0 1
//- ||||
#define BSP0_RCR2 0x81a1 //===========================================================================
XCR1
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 xx XFRLEN1-6 ------ XFRLEN1-4 |
0 0 0 0
//- |+--- 0 XFRLEN1-3 --------------- XFRLEN1-0 |
0 0 0 0
//- ||+-- 4 XWDLEN1-2 ----- XWDLEN1-0 xx |
1 0 1 0
//- |||+- 0 xx xx xx xx |
0 0 0 0
//- ||||
#define BSP0_XCR1 0x0000

//===========================================================================
XCR2
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 XPHASE XFRLEN2-6 ------- XFRLEN2-4 |
0 0 0 0
//- |+--- 0 XFRLEN2-3 --------------- XFRLEN2-0 |
0 0 0 0
//- ||+-- 0 XWDLEN2 -------- XWDLEN2 XCOMPAND |
1 0 1 0
//- |||+- 1 XCOMPAND XFIG -- XDATDLY -- |
0 0 0 0
//- ||||
#define BSP0_XCR2 0x0000

//===========================================================================
SRGR1
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- 0 FWID-15 -------------------------- |
0 0 0 0
//- |+--- 0 -------------------------- FWID-0 |
0 0 0 0
//- ||+-- 0 CLKGDV-7 ------------------------- |
0 0 0 0
//- |||+- 0 ------------------------- CLKDV-0 |
0 0 0 0
//- ||||
#define BSP0_SRGR1 0x0000 //===========================================================================
SRGR2
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- X GSYNC CLKSP CLKSM FSGM |
0 1 0 1
//- |+--- 0 FPER-11 ------------------------- |
0 0 0 0
//- ||+-- 0 -------------------------------- |
0 0 0 0
//- |||+- 0 -------------------------- FPER-0 |
0 0 0 0
//- ||||
#define BSP0_SRGR2 0x5000

//===========================================================================
PCR
//- | MSB | | | LSB |
MSB LSB
//-
---------------------------------------------------
//- +---- x xx IDLEEN XIOEN RIOEN |
0 0 0 0
//- |+--- x FSXM FSRM CLKXM CLKRM |
0 0 0 0
//- ||+-- x SCLKME CLKSSTAT DXSTAT DRSTAT |
1 0 0 0
//- |||+- x FSXP FSRP CLKXP CLKRP |
0 1 0 1
//- ||||

#define BSP0_PCR 0x0085

//#define BSP0_PCR 0x1000 //as io ====================================================================
====================================================================
--- In , Harland Christofferson <harland@z...> wrote:
>
> can you furnish mcbsp register configuration info?
>
> At Tuesday, 18 January 2005, "peejayblack" <peejayblack@y...>
> wrote:
>
> >Hello,
> >I've been having difficulty with a McBSP interface. It's
> >connected to a
> >I2S A-D converter set up as a master. I.e. it generates the bit clock
> >and frame sync. I'm receiving only so the A-D just pumps the clock
> >out.
> >
> >I can get the receive to fire an interrupt, but all I read out of the
> >DRR's is zero.
> >I do have the proper signals clocking in ( Viewed on a scope ) The
> >inputs seem ok as I reprogrammed the receive lines as input ports and
> >I'm able to read them. I read the DRR's in the proper
> >sequence 2 then 1.
> >
> >Since the A-D converter is generating all the clocks I really
> >don't
> >need to be to very concerned about the clock generator …or do
> >I??? My
> >assumption is based on SPRA595. Its for the c6000 but the McBSP are
> >very similar.
> >
> >Any Ideas ?
> >peejayblack
> >
> ----------------------------------------------------------------------
> Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems
>
> http://www.zerocrossings.com/





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