Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).
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Re: hi [C55x algorithms in 65 nm process] - Jeff Brower - Nov 18 14:11:00 2005
Sateesh-
> i'm working on c55x dsp series architecture modifications .
> My plan is to implement on 65 nm technology.
> every architecture is designed for 1 perticular technology.
> by seeing architecture shall we find technolgy?
> previously it is 180,130,90,65,45nms....it depends on masks or any other?
I think you may have wanted to post this to the C55x group.
-Jeff
> > -----Original Message-----
> > From: jbrower@jbro...
> > Sent: Fri, 18 Nov 2005 11:15:08 -0600
> > To: schuster@schu...
> > Subject: Re: [c55x] EMIF performance
> >
> > Michael-
> >
> >>> Did TI mention 5502? What about with cache enabled -- still that slow?
> >>> Can you tell me which TI person you were talking to?
> >> well cache enabling does not help. We have to read data from a
> >> AD-Converter,
> >> and store it back to a sdram, so a cache won't help (?).
> >
> > SDRAM or SRAM? Your comment referred to "async EMIF" -- that's not an
> > SDRAM.
> >
> >> No, the 5502 was not recommend to us by TI Epic Center (I don't want to
> >> publish a name on this here).
> >
> > That's fine, but in that case can you ask them if it's Ok? Or ask them
> > to send
> > e-mail to me so I can continue the dialog? There is confusion here that
> > I want to
> > resolve. Thanks.
> >
> > -Jeff

(You need to be a member of c55x -- send a blank email to c55x-subscribe@yahoogroups.com )
Re: hi [C55x algorithms in 65 nm process] - Jeff Brower - Nov 18 14:12:00 2005
Sateesh-
> i'm working on c55x dsp series architecture modifications .
> My plan is to implement on 65 nm technology.
> every architecture is designed for 1 perticular technology.
> by seeing architecture shall we find technolgy?
> previously it is 180,130,90,65,45nms....it depends on masks or any other?
I think you may have wanted to post this to the C55x group.
-Jeff
> > -----Original Message-----
> > From: jbrower@jbro...
> > Sent: Fri, 18 Nov 2005 11:15:08 -0600
> > To: schuster@schu...
> > Subject: Re: [c55x] EMIF performance
> >
> > Michael-
> >
> >>> Did TI mention 5502? What about with cache enabled -- still that slow?
> >>> Can you tell me which TI person you were talking to?
> >> well cache enabling does not help. We have to read data from a
> >> AD-Converter,
> >> and store it back to a sdram, so a cache won't help (?).
> >
> > SDRAM or SRAM? Your comment referred to "async EMIF" -- that's not an
> > SDRAM.
> >
> >> No, the 5502 was not recommend to us by TI Epic Center (I don't want to
> >> publish a name on this here).
> >
> > That's fine, but in that case can you ask them if it's Ok? Or ask them
> > to send
> > e-mail to me so I can continue the dialog? There is confusion here that
> > I want to
> > resolve. Thanks.
> >
> > -Jeff

(You need to be a member of c55x -- send a blank email to c55x-subscribe@yahoogroups.com )