Hi all,

I'm new to this usergroup, so please forgive any break from etiquette.

I am looking to utilise the DMA controller on the C5510 to perform 
bulk transfers between two peripherals, a Compact Flash card and a USB 
controller chip.

DSPs I have used in the past allow the data transfer flow to/from 
peripherals to be controlled by the DREQ/DACK hardware signals on the 
DSP. However, I cannot seem to see the same flow control available on 
the C5510.

Am I just not looking hard enough, or does this DSP employ a different 
mechanism for DMA flow control ?

Cheers in advance for any response.

Scottie

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hi Scottie,

There is an on-chip dma controller for c5510.
This is user programmable to transfer data between an
external  device(that is interfaced to dsp through
EMIF) and the internal memory. 
Refer the following docs for details:
DMA refernce guide:
http://focus.ti.com/lit/ug/spru587d/spru587d.pdf
emif reference guide:
http://focus.ti.com/lit/ug/spru590/spru590.pdf

There are no external hardware pins analogous to
DREQ/DACK in c5510dsp chip.

regards,
Dileepan.
--- smiffoz <s...@yahoo.co.uk> wrote:

> Hi all,
> 
> I'm new to this usergroup, so please forgive any
> break from etiquette.
> 
> I am looking to utilise the DMA controller on the
> C5510 to perform 
> bulk transfers between two peripherals, a Compact
> Flash card and a USB 
> controller chip.
> 
> DSPs I have used in the past allow the data transfer
> flow to/from 
> peripherals to be controlled by the DREQ/DACK
> hardware signals on the 
> DSP. However, I cannot seem to see the same flow
> control available on 
> the C5510.
> 
> Am I just not looking hard enough, or does this DSP
> employ a different 
> mechanism for DMA flow control ?
> 
> Cheers in advance for any response.
> 
> Scottie
__________________________________________________

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Hi Dileepan,

Thanks for the response.

On investigating these documents, I noticed that DMA Channel Control 
Register (DMACCR) can be used to specify a sync event e.g. An IRQ 
line, etc. Can this be used to control the transfer flow ?

I am concerned that my external device has a small FIFO buffer and, 
if the 5510 offers no hardware control pins for DMA tranfers, how do 
I stop it writing to the FIFO on the external device when it is 
full ?

Cheers,

Scott

--- In c...@yahoogroups.com, Dileepan C <dileepan_c@...> wrote:
>
> hi Scottie,
> 
> There is an on-chip dma controller for c5510.
> This is user programmable to transfer data between an
> external  device(that is interfaced to dsp through
> EMIF) and the internal memory. 
> Refer the following docs for details:
> DMA refernce guide:
> http://focus.ti.com/lit/ug/spru587d/spru587d.pdf
> emif reference guide:
> http://focus.ti.com/lit/ug/spru590/spru590.pdf
> 
> There are no external hardware pins analogous to
> DREQ/DACK in c5510dsp chip.
> 
> regards,
> Dileepan.
> --- smiffoz <smiffoz@...> wrote:
> 
> > Hi all,
> > 
> > I'm new to this usergroup, so please forgive any
> > break from etiquette.
> > 
> > I am looking to utilise the DMA controller on the
> > C5510 to perform 
> > bulk transfers between two peripherals, a Compact
> > Flash card and a USB 
> > controller chip.
> > 
> > DSPs I have used in the past allow the data transfer
> > flow to/from 
> > peripherals to be controlled by the DREQ/DACK
> > hardware signals on the 
> > DSP. However, I cannot seem to see the same flow
> > control available on 
> > the C5510.
> > 
> > Am I just not looking hard enough, or does this DSP
> > employ a different 
> > mechanism for DMA flow control ?
> > 
> > Cheers in advance for any response.
> > 
> > Scottie

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

Scott-

> On investigating these documents, I noticed that DMA Channel Control
> Register (DMACCR) can be used to specify a sync event e.g. An IRQ
> line, etc. Can this be used to control the transfer flow ?

Yes.

> I am concerned that my external device has a small FIFO buffer and,
> if the 5510 offers no hardware control pins for DMA tranfers, how do
> I stop it writing to the FIFO on the external device when it is
> full ?

One way is if you connect your peripheral to the C5510 memory interface
(EMIF) as an asynchronous device.  Then you can use ARDY signal to allow
your device to indicate to the C5510 when ready, and if not (busy) then
the C5510 will wait.  DMA transfers between internal C55x memory and EMIF
locations used by your peripheral will take this into account.

This method is only good if your peripheral has a typical parallel "memory
style" interface with R/W line, chip-enable, etc.

-Jeff

> --- In c...@yahoogroups.com, Dileepan C <dileepan_c@...> wrote:
>>
>> hi Scottie,
>>
>> There is an on-chip dma controller for c5510.
>> This is user programmable to transfer data between an
>> external  device(that is interfaced to dsp through
>> EMIF) and the internal memory.
>> Refer the following docs for details:
>> DMA refernce guide:
>> http://focus.ti.com/lit/ug/spru587d/spru587d.pdf
>> emif reference guide:
>> http://focus.ti.com/lit/ug/spru590/spru590.pdf
>>
>> There are no external hardware pins analogous to
>> DREQ/DACK in c5510dsp chip.
>>
>> regards,
>> Dileepan.
>> --- smiffoz <smiffoz@...> wrote:
>>
>> > Hi all,
>> >
>> > I'm new to this usergroup, so please forgive any
>> > break from etiquette.
>> >
>> > I am looking to utilise the DMA controller on the
>> > C5510 to perform
>> > bulk transfers between two peripherals, a Compact
>> > Flash card and a USB
>> > controller chip.
>> >
>> > DSPs I have used in the past allow the data transfer
>> > flow to/from
>> > peripherals to be controlled by the DREQ/DACK
>> > hardware signals on the
>> > DSP. However, I cannot seem to see the same flow
>> > control available on
>> > the C5510.
>> >
>> > Am I just not looking hard enough, or does this DSP
>> > employ a different
>> > mechanism for DMA flow control ?
>> >
>> > Cheers in advance for any response.
>> >
>> > Scottie

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

Jeff,

Thanks for the advice, the ARDY signal will come in very useful in 
future. However, for my current system, I wish to perform DMA's 
between two peripherals on the EMIF, both of which have signals to 
indicate their FIFO statusand , as there is only a single ARDY 
signal, I don't think it would work for this particular system.

Going back to the DMA Channel sync event, if I specify that INT5 for 
example, should be used to sync a particular DMA transfer - does 
that mean the DMA channel will check the status of the INT5 signal 
before prior to every read/write transaction ? Or will it only check 
the status once at the start and then perform the entire data 
transfer ?

Also, if the DMA is synced to INT5, would I still have to service 
INT5 normally or, if I masked it, would the DMA channel still 
respond to it status ?

Thanks again for your help,

Scottie

--- In c...@yahoogroups.com, "Jeff Brower" <jbrower@...> wrote:
>
> Scott-
> 
> > On investigating these documents, I noticed that DMA Channel 
Control
> > Register (DMACCR) can be used to specify a sync event e.g. An IRQ
> > line, etc. Can this be used to control the transfer flow ?
> 
> Yes.
> 
> > I am concerned that my external device has a small FIFO buffer 
and,
> > if the 5510 offers no hardware control pins for DMA tranfers, 
how do
> > I stop it writing to the FIFO on the external device when it is
> > full ?
> 
> One way is if you connect your peripheral to the C5510 memory 
interface
> (EMIF) as an asynchronous device.  Then you can use ARDY signal to 
allow
> your device to indicate to the C5510 when ready, and if not (busy) 
then
> the C5510 will wait.  DMA transfers between internal C55x memory 
and EMIF
> locations used by your peripheral will take this into account.
> 
> This method is only good if your peripheral has a typical 
parallel "memory
> style" interface with R/W line, chip-enable, etc.
> 
> -Jeff
> 
> > --- In c...@yahoogroups.com, Dileepan C <dileepan_c@> wrote:
> >>
> >> hi Scottie,
> >>
> >> There is an on-chip dma controller for c5510.
> >> This is user programmable to transfer data between an
> >> external  device(that is interfaced to dsp through
> >> EMIF) and the internal memory.
> >> Refer the following docs for details:
> >> DMA refernce guide:
> >> http://focus.ti.com/lit/ug/spru587d/spru587d.pdf
> >> emif reference guide:
> >> http://focus.ti.com/lit/ug/spru590/spru590.pdf
> >>
> >> There are no external hardware pins analogous to
> >> DREQ/DACK in c5510dsp chip.
> >>
> >> regards,
> >> Dileepan.
> >>
> >>
> >> --- smiffoz <smiffoz@> wrote:
> >>
> >> > Hi all,
> >> >
> >> > I'm new to this usergroup, so please forgive any
> >> > break from etiquette.
> >> >
> >> > I am looking to utilise the DMA controller on the
> >> > C5510 to perform
> >> > bulk transfers between two peripherals, a Compact
> >> > Flash card and a USB
> >> > controller chip.
> >> >
> >> > DSPs I have used in the past allow the data transfer
> >> > flow to/from
> >> > peripherals to be controlled by the DREQ/DACK
> >> > hardware signals on the
> >> > DSP. However, I cannot seem to see the same flow
> >> > control available on
> >> > the C5510.
> >> >
> >> > Am I just not looking hard enough, or does this DSP
> >> > employ a different
> >> > mechanism for DMA flow control ?
> >> >
> >> > Cheers in advance for any response.
> >> >
> >> > Scottie
>

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

Scott-

> Thanks for the advice, the ARDY signal will come in very useful in
> future. However, for my current system, I wish to perform DMA's
> between two peripherals on the EMIF, both of which have signals to
> indicate their FIFO statusand , as there is only a single ARDY
> signal, I don't think it would work for this particular system.

You have to AND the RDY signals on your peripherals together.  If either one is low,
then the C55x EMIF will wait.  By definition only one of your peripherals can be
accessed by the EMIF at one time.

> Going back to the DMA Channel sync event, if I specify that INT5 for
> example, should be used to sync a particular DMA transfer - does
> that mean the DMA channel will check the status of the INT5 signal
> before prior to every read/write transaction ? Or will it only check
> the status once at the start and then perform the entire data
> transfer ?
> 
> Also, if the DMA is synced to INT5, would I still have to service
> INT5 normally or, if I masked it, would the DMA channel still
> respond to it status ?

I haven't used external DMA on EMIF for a while -- normally I have just SDRAM and
Flash there, and hook the fast "bursty" peripherals to things like McBSP, UTOPIA,
HPI, etc.  However, I would think that in your case you would use an INTn signal to
tell you when a DMA buffer is completed, and let the EMIF handle peripheral
handshaking the way it was designed -- which means in the case of async devices, use
ARDY.

-Jeff

> --- In c...@yahoogroups.com, "Jeff Brower" <jbrower@...> wrote:
> >
> > Scott-
> >
> > > On investigating these documents, I noticed that DMA Channel
> Control
> > > Register (DMACCR) can be used to specify a sync event e.g. An IRQ
> > > line, etc. Can this be used to control the transfer flow ?
> >
> > Yes.
> >
> > > I am concerned that my external device has a small FIFO buffer
> and,
> > > if the 5510 offers no hardware control pins for DMA tranfers,
> how do
> > > I stop it writing to the FIFO on the external device when it is
> > > full ?
> >
> > One way is if you connect your peripheral to the C5510 memory
> interface
> > (EMIF) as an asynchronous device.  Then you can use ARDY signal to
> allow
> > your device to indicate to the C5510 when ready, and if not (busy)
> then
> > the C5510 will wait.  DMA transfers between internal C55x memory
> and EMIF
> > locations used by your peripheral will take this into account.
> >
> > This method is only good if your peripheral has a typical
> parallel "memory
> > style" interface with R/W line, chip-enable, etc.
> >
> > -Jeff
> >
> > > --- In c...@yahoogroups.com, Dileepan C <dileepan_c@> wrote:
> > >>
> > >> hi Scottie,
> > >>
> > >> There is an on-chip dma controller for c5510.
> > >> This is user programmable to transfer data between an
> > >> external  device(that is interfaced to dsp through
> > >> EMIF) and the internal memory.
> > >> Refer the following docs for details:
> > >> DMA refernce guide:
> > >> http://focus.ti.com/lit/ug/spru587d/spru587d.pdf
> > >> emif reference guide:
> > >> http://focus.ti.com/lit/ug/spru590/spru590.pdf
> > >>
> > >> There are no external hardware pins analogous to
> > >> DREQ/DACK in c5510dsp chip.
> > >>
> > >> regards,
> > >> Dileepan.
> > >>
> > >>
> > >> --- smiffoz <smiffoz@> wrote:
> > >>
> > >> > Hi all,
> > >> >
> > >> > I'm new to this usergroup, so please forgive any
> > >> > break from etiquette.
> > >> >
> > >> > I am looking to utilise the DMA controller on the
> > >> > C5510 to perform
> > >> > bulk transfers between two peripherals, a Compact
> > >> > Flash card and a USB
> > >> > controller chip.
> > >> >
> > >> > DSPs I have used in the past allow the data transfer
> > >> > flow to/from
> > >> > peripherals to be controlled by the DREQ/DACK
> > >> > hardware signals on the
> > >> > DSP. However, I cannot seem to see the same flow
> > >> > control available on
> > >> > the C5510.
> > >> >
> > >> > Am I just not looking hard enough, or does this DSP
> > >> > employ a different
> > >> > mechanism for DMA flow control ?
> > >> >
> > >> > Cheers in advance for any response.
> > >> >
> > >> > Scottie
> >

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Jeff,
   
  Thanks again for your help. AND'ing the RDY signals would work apart from one particular
instance I can think of.
   
  For example, if I am reading from one device (RP) using its 'Data Ready' signal and writing
to another device (WP), using its 'Ready to RX' signal, the data transfer should work well up
until the point where RP spits out its last few bytes and de-asserts 'Data Ready'. This would
cause the EMIFs ARDY to be de-asserted, which could possibly prevent the last few bytes being
written to WP, even although its asserting 'Ready to RX'. Does that hold true ?
   
  You mentioned that you sometimes hang peripherals of the HPI, as I've only ever used a Host
Port in the past to connect to a host processor, I've never considered this an option.
   
  I'm trying to configure a system where I store data on a CompactFlash card and at a later
date, I want to read this data from Compact Flash and upload it to a PC via a USB Peripheral
Controller, using the DMA controller.
   
  I initially envisaged hanging both the Compact Flash and USB Peripheral Controller off of the
C55x EMIF, but maybe I should start looking at the HPI. Do you think it would lend itself well
to such peripherals ?
   
  Cheers again,
   
  Scottie

Jeff Brower <jbrower@xxx> wrote:
  Scott-

> Thanks for the advice, the ARDY signal will come in very useful in
> future. However, for my current system, I wish to perform DMA's
> between two peripherals on the EMIF, both of which have signals to
> indicate their FIFO statusand , as there is only a single ARDY
> signal, I don't think it would work for this particular system.

You have to AND the RDY signals on your peripherals together. If either one is low,
then the C55x EMIF will wait. By definition only one of your peripherals can be
accessed by the EMIF at one time.

> Going back to the DMA Channel sync event, if I specify that INT5 for
> example, should be used to sync a particular DMA transfer - does
> that mean the DMA channel will check the status of the INT5 signal
> before prior to every read/write transaction ? Or will it only check
> the status once at the start and then perform the entire data
> transfer ?
> 
> Also, if the DMA is synced to INT5, would I still have to service
> INT5 normally or, if I masked it, would the DMA channel still
> respond to it status ?

I haven't used external DMA on EMIF for a while -- normally I have just SDRAM and
Flash there, and hook the fast "bursty" peripherals to things like McBSP, UTOPIA,
HPI, etc. However, I would think that in your case you would use an INTn signal to
tell you when a DMA buffer is completed, and let the EMIF handle peripheral
handshaking the way it was designed -- which means in the case of async devices, use
ARDY.

-Jeff

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

Scott-

>   Thanks again for your help. AND'ing the RDY signals would work apart
> from one particular instance I can think of.
>
>   For example, if I am reading from one device (RP) using its 'Data
> Ready'
> signal and writing to another device (WP), using its 'Ready to RX'
> signal, the data transfer should work well up until the point where RP
> spits out its last few bytes and de-asserts 'Data Ready'. This would
> cause the EMIFs ARDY to be de-asserted, which could possibly prevent the
> last few bytes being written to WP, even although its asserting 'Ready
> to RX'. Does that hold true ?

Hmmm... maybe I'm not understanding something.  Are you trying to get
peripherals to talk to *each other* and *also* talk to the C55x EMIF?  If
so that's a different ballgame.  In that case you need HOLD/HOLDA to allow
peripherals to request the EMIF bus for some time for their own purposes.

If not, then AND'ing RDY signals should be sufficient because your DSP
code "knows" what to expect -- it initiates transfers between with each
peripheral (based on interrupt for RP), so it knows how many words are
needed before it starts something with another peripheral.

>   You mentioned that you sometimes hang peripherals of the HPI, as I've
> only ever used a Host Port in the past to connect to a host processor,
> I've never considered this an option.

HPI is strictly a 'slave' peripheral -- external devices control both
read/write transfers.  What we've done before is hook up DMA controllers,
for example FPGA logic, that can be started at DSP code request (via
interrupt).  The DMA controller reads a pre-defined DSP memory area to
learn the transfer parameters specified the requesting DSP, then uses HPI
to move the data.  Multiple DSPs and multiple peripherals can transfer
data this way.

-Jeff

>   I'm trying to configure a system where I store data on a CompactFlash
> card and at a later date, I want to read this data from Compact Flash
> and upload it to a PC via a USB Peripheral Controller, using the DMA
> controller.
>
>   I initially envisaged hanging both the Compact Flash and USB Peripheral
> Controller off of the C55x EMIF, but maybe I should start looking at the
> HPI. Do you think it would lend itself well to such peripherals ?
>
>   Cheers again,
>
>   Scottie
>
> Jeff Brower <jbrower@xxx> wrote:
>   Scott-
>
>> Thanks for the advice, the ARDY signal will come in very useful in
>> future. However, for my current system, I wish to perform DMA's
>> between two peripherals on the EMIF, both of which have signals to
>> indicate their FIFO statusand , as there is only a single ARDY
>> signal, I don't think it would work for this particular system.
>
> You have to AND the RDY signals on your peripherals together. If either
> one is low,
> then the C55x EMIF will wait. By definition only one of your peripherals
> can be
> accessed by the EMIF at one time.
>
>> Going back to the DMA Channel sync event, if I specify that INT5 for
>> example, should be used to sync a particular DMA transfer - does
>> that mean the DMA channel will check the status of the INT5 signal
>> before prior to every read/write transaction ? Or will it only check
>> the status once at the start and then perform the entire data
>> transfer ?
>>
>> Also, if the DMA is synced to INT5, would I still have to service
>> INT5 normally or, if I masked it, would the DMA channel still
>> respond to it status ?
>
> I haven't used external DMA on EMIF for a while -- normally I have just
> SDRAM and
> Flash there, and hook the fast "bursty" peripherals to things like McBSP,
> UTOPIA,
> HPI, etc. However, I would think that in your case you would use an INTn
> signal to
> tell you when a DMA buffer is completed, and let the EMIF handle
> peripheral
> handshaking the way it was designed -- which means in the case of async
> devices, use
> ARDY.
>
> -Jeff

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