Hello!

I am trying to get McBSP1 on my C5509A to behave as an interrupt-driven SPI slave device. I am
experienced with this DSP (using it for 1.5 years now), but this seemingly simple setup is
stumping me. I would very much appreciate any help a DSP Related user could give me.

**********Goal (For Debugging)**********
- On each frame transmitted by the master (FSX low and 8-bits clocked out), the DSP should
transmit a preset value (0xAA chosen arbitrarily).
- On each frame the DSP will check the value received from the master and compare it to an
expected value (0x18 chosen arbitrarily). If the values match, an I/O line will change state
(for debugging).

Simple, right?

**********Currently**********
- My XRDY and RRDY interrupt handlers “fire” once each per frame. XRDY fires somewhere in the
middle of the clocking sequence (I believe after the previously loaded DXR is transferred to
DSR). RRDY fires after FSX returns to high (inactive).
- The DSP transmits “junk” to the master each frame, but this junk is somewhat correlated to
the value that the master sent. This means that for any given value I have the master send to
the DSP, the DSP responds with a distinct “set” of junk what looks like a random order.

For example:
Value Sent: 0xAA
DSP transmits (not in order): 0x20, 0x40, 0x50, 0x54, 0x5F, 0x94
Value Sent: 0x18
DSP transmits: 0x00, 0x3F, 0x40, 0x80

- My test to check if the DSP’s received value was 0x18 passes only occasionally, though I send
it 0x18 each frame.

Interestingly, the test only seems to pass on frames when the DSP transmits 0x40 (in response
to the master’s 0x18).

**********Hardware Connection**********
CLKX1 <--- SCK
DX1 ---> MISO
DR1 <--- MOSI
FSX <--- /SS
- SCK rate is 4 MHz. I’ve tried 250 kHz as well.
- Data is to be sampled on rising edges of CLKX, shifts out next bit on falling edges.

**********Setup Procedure**********
/* ***************************************************************** */
	// initialize the chip support libraries
	CSL_init();
	
	// configure PLL and set frequency
	PLL_config(&PLLStdConfig);
	
	// temporarily disable all maskable interrupts
	OldINTM = IRQ_globalDisable();
	
	// set IVPH/IVPD to start of interrupt vector table
	IRQ_setVecs((Uint32)(&VECSTART));
/* ***************************************************************** */
	// setup GPIO registers
	PCBSetup();

/* ***************************************************************** */
	// open McBSP1 for communications and hold it in reset
	hMCBSP1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);

	// program the McBSP1 control registers
	MCBSP_config(hMCBSP1, &McBSP1ConfigStructure);

	// get event IDs for interrupt setup
	Port1RXEventID = MCBSP_getRcvEventId(hMCBSP1);
	Port1TXEventID = MCBSP_getXmtEventId(hMCBSP1);

	// insert SPI interrupts into the vector table
	IRQ_plug(Port1RXEventID, &SpiRxIsr);
	IRQ_plug(Port1TXEventID, &SpiTxIsr);
	
	// enable interrupts
	IRQ_enable(Port1RXEventID);
	IRQ_enable(Port1TXEventID);

	// set initial values
	DXR1_1_R = 0xAAAA;
	SpiTxVal = 0;
	SPITxBegin = 0;

	// start SRG
	MCBSP_start(hMCBSP1, MCBSP_SRGR_START, 0x00AA);

	// start transmitter and receiver
	MCBSP_start(hMCBSP1, MCBSP_XMIT_START | MCBSP_RCV_START, 0x00AA);

	// enable all maskable interrupts
	IRQ_globalEnable();

**********Interrupt Handlers**********
//*********************************************************************//
interrupt void SpiTxIsr(void)
//*********************************************************************//
{
	MCBSP_write16(hMCBSP1, 0xAAAA);
}
//*********************************************************************//
interrupt void SpiRxIsr(void)
//*********************************************************************//
{
	SpiTxVal = MCBSP_read16(hMCBSP1);

	if ((SpiTxVal & 0x00FF) == 0x0018)
	{
		SPITxBegin = !SPITxBegin;

		if (SPITxBegin)
			AGPIODATA_R |= AGPIO_9;
		else
			AGPIODATA_R &= ~AGPIO_9;
	}
}

**********Configuration Structure (With Notes)**********
I’ve noted here what each bit should do, which bits are required according to the McBSP User
Guide for SPI Slave mode, and which bits should be Not Applicable due to other settings.

// SPI Serial Port for External Communications (Interrupt-Driven Slave)
MCBSP_Config 	McBSP1ConfigStructure = {
		0x1800,		// SPCR1
		0x0000,		// SPCR2
		0x0000,		// RCR1
		0x0000,		// RCR2
		0x0000,		// XCR1
		0x0000,		// XCR2
		0x0001,		// SRGR1
		0x2000,		// SRGR2
		0x0000,		// MCR1
		0x0000,		// MCR2
		0x000D,		// PCR
		0x0000,		// RCERA
		0x0000,		// RCERB
		0x0000,		// RCERC
		0x0000,		// RCERD
		0x0000,		// RCERE
		0x0000,		// RCERF
		0x0000,		// RCERG
		0x0000,		// RCERH
		0x0000,		// XCERA
		0x0000,		// XCERB
		0x0000,		// XCERC
		0x0000,		// XCERD
		0x0000,		// XCERE
		0x0000,		// XCERF
		0x0000,		// XCERG
		0x0000		// XCERH
		};
// ***SPCR1_1_R = 0x1800***
//	* 0 DLB: no digital loopback
//	0 0 RJUST: right justify, unsigned data
//	1 * 1 CLKSTP: clock stop mode, half-cycle delay (***REQUIRED***)
//	0 0 0 NA
//	* 0 DXENA: first-bit DX delay off
//	0 NA
//	0 0 RINTM: RINT on RRDY (0->1)
//	* 0 RSYNCERR: rx frame sync error status
//	0 RFULL: rx full error status
//	0 RRDY: rx ready status	(DRR1 read to clear)
//	0 RRST: hold rx in reset
// ***SPCR2_1_R = 0x0000***
//	* 0 0 0 0 * 0 0 NA
//	0 FREE: module stops running during emulation break
//	0 SOFT: hard stop duing emulation break
//	* 0 FRST: hold frame sync logic in reset
//	0 GRST: hold sample rate generator (SRG) in reset
//	0 0 XINTM: XINT on XRDY (0->1)
//	* 0 XYNCERR: tx frame sync error status
//	0 XEMPTY: tx empty error status
//	0 XRDY: tx ready status (DXR1 load to clear)
//	0 XRST: hold tx in reset
// ***RCR1_1_R = 0x0000***
//	* 0 NA
//	0 0 0 * 0 0 0 0 RFRLEN1: rx frame 1 length = 1 word (***REQUIRED***)
//	* 0 0 0 RWDLEN1: rx word length = 8 bits (***REQUIRED (same as XWDLEN1)***)
//	0 * 0 0 0 0 NA
// ***RCR2_1_R = 0x0000***
//	* 0 RPHASE: single phase frame (turns off phase 2) (***REQUIRED***)	
//	0 0 0 * 0 0 0 0 RFRLEN2: rx frame 2 length = 1 word (NA)
//	* 0 0 0 RWDLEN2: rx word length = 8 bits (NA)
//	0 * 0 RCOMPAND: no companding, MSB first
//	0 RFIG: FSR pulse causes RSR to be discarded; begin new rx
//	0 0 RDATDLY: 0-bit delay between frame sync and reception (***REQUIRED***)
// ***XCR1_1_R = 0x0000***
//	* 0 NA
//	0 0 0 * 0 0 0 0 XFRLEN1: tx frame 1 length = 1 word (***REQUIRED***)
//	* 0 0 0 XWDLEN1: tx word length = 8 bits (***REQUIRED (same as RWDLEN1)***)
//	0 * 0 0 0 0 NA
// ***XCR2_1_R = 0x0000***
//	* 0 XPHASE: single phase frame (turns off phase 2) (***REQUIRED***)	
//	0 0 0 * 0 0 0 0 XFRLEN2: tx frame 2 length = 1 word (NA)
//	* 0 0 0 XWDLEN2: tx word length = 8 bits (NA)
//	0 * 0 XCOMPAND: no companding, MSB first
//	0 XFIG: FSX pulse causes XSR to be discarded; begin new tx
//	0 0 XDATDLY: 0-bit delay between frame sync and transmission (***REQUIRED***)
// ***SRGR1_1_R = 0x0001***
//	* 0 0 0 0 * 0 0 0 0 FWID: frame sync pulse width = 1 CLKG cycle	(NA; FS external)
//	* 0 0 0 0 * 0 0 0 1 CLKGDV: McBSP internal input clock / 2 for CLKG (***REQUIRED***)
// ***SRGR2_1_R = 0x2000***
//	* 0 GSYNC: no clock sync to CLKS or CLKR (NA; FSR internally connected)
//	0 CLKSP: CLKS pin rising edge triggered (NA; no CLKS)
//	1 CLKSM: input clock from McBSP internal input clock (CLKX) (***REQUIRED***)
//	0 FSGM: FSX when DXR copied to XSR (NA; FSXM = 0)	
//	* 0 0 0 0 * 0 0 0 0 * 0 0 0 0 FPER: frame sync period = FPER + 1 CLKG cycles (NA)
// ***PCR1_R = 0x000D***
//	* 0 NA
//	0 IDLEEN: McBSP remains active during idle
//	0 XIOEN: transmitter pins are set as serial port pins
//	0 RIOEN: receiver pins are set as serial port pins
//	* 0 FSXM: FSX input, driven by SPI master (***REQUIRED***)
//	0 FSRM: FSR input, driven by SPI master (NA; FSR internally connected)	
//	0 CLKXM: CLKX input, driven by master; CLKR driven internally by CLKX (***REQUIRED***)
//	0 CLKRM: CLKR input, driven by master (NA; CLKR intenally connected)
//	* 0 SCLKME: SRG clock derived from McBSP internal input clock (CLKX) (***REQUIRED***)
//	0 CLKSTAT: CLKS status (NA; no CLKS)
//	0 DXSTAT: drive DX pin (NA; serial port mode)
//	0 DRSTAT: drive DR pin (NA; serial port mode)
//	* 1 FSXP: tx frame sync polarity = active low (***REQUIRED***)
//	1 FSRP: rx frame sync polarity = active low (NA???)
//	0 CLKXP: tx data on CLKX rising edge (***REQUIRED***)
//	1 CLKRP: rx data on CLKX rising edge (***REQUIRED***)

Thank you for reading!

Craig Neely

c...@centeye.com

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

Hi,

   The best way to solve the problem is, with the same setting you enable
DLB(Digital Loop Back Mode) and check out are you getting data back what you
have sent. This procedure confirms McBSP is working.

Rgds
-Prasad 

-----Original Message-----
From: c...@yahoogroups.com [mailto:c...@yahoogroups.com] On Behalf Of
c...@centeye.com
Sent: Saturday, June 17, 2006 6:10 AM
To: c...@yahoogroups.com
Subject: [c55x] McBSP as an Interrupt-Driven SPI Slave

Hello!

I am trying to get McBSP1 on my C5509A to behave as an interrupt-driven SPI
slave device. I am experienced with this DSP (using it for 1.5 years now),
but this seemingly simple setup is stumping me. I would very much appreciate
any help a DSP Related user could give me.

**********Goal (For Debugging)**********
- On each frame transmitted by the master (FSX low and 8-bits clocked out),
the DSP should transmit a preset value (0xAA chosen arbitrarily).
- On each frame the DSP will check the value received from the master and
compare it to an expected value (0x18 chosen arbitrarily). If the values
match, an I/O line will change state (for debugging).

Simple, right?

**********Currently**********
- My XRDY and RRDY interrupt handlers "fire" once each per frame. XRDY fires
somewhere in the middle of the clocking sequence (I believe after the
previously loaded DXR is transferred to DSR). RRDY fires after FSX returns to
high (inactive).
- The DSP transmits "junk" to the master each frame, but this junk is
somewhat correlated to the value that the master sent. This means that for
any given value I have the master send to the DSP, the DSP responds with a
distinct "set" of junk what looks like a random order.

For example:
Value Sent: 0xAA
DSP transmits (not in order): 0x20, 0x40, 0x50, 0x54, 0x5F, 0x94
Value Sent: 0x18
DSP transmits: 0x00, 0x3F, 0x40, 0x80

- My test to check if the DSP's received value was 0x18 passes only
occasionally, though I send it 0x18 each frame.

Interestingly, the test only seems to pass on frames when the DSP transmits
0x40 (in response to the master's 0x18).

**********Hardware Connection**********
CLKX1 <--- SCK
DX1 ---> MISO
DR1 <--- MOSI
FSX <--- /SS
- SCK rate is 4 MHz. I've tried 250 kHz as well.
- Data is to be sampled on rising edges of CLKX, shifts out next bit on
falling edges.

**********Setup Procedure**********
/* ***************************************************************** */
	// initialize the chip support libraries
	CSL_init();
	
	// configure PLL and set frequency
	PLL_config(&PLLStdConfig);
	
	// temporarily disable all maskable interrupts
	OldINTM = IRQ_globalDisable();
	
	// set IVPH/IVPD to start of interrupt vector table
	IRQ_setVecs((Uint32)(&VECSTART));
/* ***************************************************************** */
	// setup GPIO registers
	PCBSetup();

/* ***************************************************************** */
	// open McBSP1 for communications and hold it in reset
	hMCBSP1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);

	// program the McBSP1 control registers
	MCBSP_config(hMCBSP1, &McBSP1ConfigStructure);

	// get event IDs for interrupt setup
	Port1RXEventID = MCBSP_getRcvEventId(hMCBSP1);
	Port1TXEventID = MCBSP_getXmtEventId(hMCBSP1);

	// insert SPI interrupts into the vector table
	IRQ_plug(Port1RXEventID, &SpiRxIsr);
	IRQ_plug(Port1TXEventID, &SpiTxIsr);
	
	// enable interrupts
	IRQ_enable(Port1RXEventID);
	IRQ_enable(Port1TXEventID);

	// set initial values
	DXR1_1_R = 0xAAAA;
	SpiTxVal = 0;
	SPITxBegin = 0;

	// start SRG
	MCBSP_start(hMCBSP1, MCBSP_SRGR_START, 0x00AA);

	// start transmitter and receiver
	MCBSP_start(hMCBSP1, MCBSP_XMIT_START | MCBSP_RCV_START, 0x00AA);

	// enable all maskable interrupts
	IRQ_globalEnable();

**********Interrupt Handlers**********
//*********************************************************************//
interrupt void SpiTxIsr(void)
//*********************************************************************//
{
	MCBSP_write16(hMCBSP1, 0xAAAA);
}
//*********************************************************************//
interrupt void SpiRxIsr(void)
//*********************************************************************//
{
	SpiTxVal = MCBSP_read16(hMCBSP1);

	if ((SpiTxVal & 0x00FF) == 0x0018)
	{
		SPITxBegin = !SPITxBegin;

		if (SPITxBegin)
			AGPIODATA_R |= AGPIO_9;
		else
			AGPIODATA_R &= ~AGPIO_9;
	}
}

**********Configuration Structure (With Notes)**********
I've noted here what each bit should do, which bits are required according to
the McBSP User Guide for SPI Slave mode, and which bits should be Not
Applicable due to other settings.

// SPI Serial Port for External Communications (Interrupt-Driven Slave)
MCBSP_Config 	McBSP1ConfigStructure = {
		0x1800,		// SPCR1
		0x0000,		// SPCR2
		0x0000,		// RCR1
		0x0000,		// RCR2
		0x0000,		// XCR1
		0x0000,		// XCR2
		0x0001,		// SRGR1
		0x2000,		// SRGR2
		0x0000,		// MCR1
		0x0000,		// MCR2
		0x000D,		// PCR
		0x0000,		// RCERA
		0x0000,		// RCERB
		0x0000,		// RCERC
		0x0000,		// RCERD
		0x0000,		// RCERE
		0x0000,		// RCERF
		0x0000,		// RCERG
		0x0000,		// RCERH
		0x0000,		// XCERA
		0x0000,		// XCERB
		0x0000,		// XCERC
		0x0000,		// XCERD
		0x0000,		// XCERE
		0x0000,		// XCERF
		0x0000,		// XCERG
		0x0000		// XCERH
		};
// ***SPCR1_1_R = 0x1800***
//	* 0 DLB: no digital loopback
//	0 0 RJUST: right justify, unsigned data
//	1 * 1 CLKSTP: clock stop mode, half-cycle delay (***REQUIRED***)
//	0 0 0 NA
//	* 0 DXENA: first-bit DX delay off
//	0 NA
//	0 0 RINTM: RINT on RRDY (0->1)
//	* 0 RSYNCERR: rx frame sync error status
//	0 RFULL: rx full error status
//	0 RRDY: rx ready status	(DRR1 read to clear)
//	0 RRST: hold rx in reset
// ***SPCR2_1_R = 0x0000***
//	* 0 0 0 0 * 0 0 NA
//	0 FREE: module stops running during emulation break
//	0 SOFT: hard stop duing emulation break
//	* 0 FRST: hold frame sync logic in reset
//	0 GRST: hold sample rate generator (SRG) in reset
//	0 0 XINTM: XINT on XRDY (0->1)
//	* 0 XYNCERR: tx frame sync error status
//	0 XEMPTY: tx empty error status
//	0 XRDY: tx ready status (DXR1 load to clear)
//	0 XRST: hold tx in reset
// ***RCR1_1_R = 0x0000***
//	* 0 NA
//	0 0 0 * 0 0 0 0 RFRLEN1: rx frame 1 length = 1 word (***REQUIRED***)
//	* 0 0 0 RWDLEN1: rx word length = 8 bits (***REQUIRED (same as
XWDLEN1)***)
//	0 * 0 0 0 0 NA
// ***RCR2_1_R = 0x0000***
//	* 0 RPHASE: single phase frame (turns off phase 2) (***REQUIRED***)

//	0 0 0 * 0 0 0 0 RFRLEN2: rx frame 2 length = 1 word (NA)
//	* 0 0 0 RWDLEN2: rx word length = 8 bits (NA)
//	0 * 0 RCOMPAND: no companding, MSB first
//	0 RFIG: FSR pulse causes RSR to be discarded; begin new rx
//	0 0 RDATDLY: 0-bit delay between frame sync and reception
(***REQUIRED***)
// ***XCR1_1_R = 0x0000***
//	* 0 NA
//	0 0 0 * 0 0 0 0 XFRLEN1: tx frame 1 length = 1 word (***REQUIRED***)
//	* 0 0 0 XWDLEN1: tx word length = 8 bits (***REQUIRED (same as
RWDLEN1)***)
//	0 * 0 0 0 0 NA
// ***XCR2_1_R = 0x0000***
//	* 0 XPHASE: single phase frame (turns off phase 2) (***REQUIRED***)

//	0 0 0 * 0 0 0 0 XFRLEN2: tx frame 2 length = 1 word (NA)
//	* 0 0 0 XWDLEN2: tx word length = 8 bits (NA)
//	0 * 0 XCOMPAND: no companding, MSB first
//	0 XFIG: FSX pulse causes XSR to be discarded; begin new tx
//	0 0 XDATDLY: 0-bit delay between frame sync and transmission
(***REQUIRED***)
// ***SRGR1_1_R = 0x0001***
//	* 0 0 0 0 * 0 0 0 0 FWID: frame sync pulse width = 1 CLKG cycle	(NA;
FS external)
//	* 0 0 0 0 * 0 0 0 1 CLKGDV: McBSP internal input clock / 2 for CLKG
(***REQUIRED***)
// ***SRGR2_1_R = 0x2000***
//	* 0 GSYNC: no clock sync to CLKS or CLKR (NA; FSR internally
connected)
//	0 CLKSP: CLKS pin rising edge triggered (NA; no CLKS)
//	1 CLKSM: input clock from McBSP internal input clock (CLKX)
(***REQUIRED***)
//	0 FSGM: FSX when DXR copied to XSR (NA; FSXM = 0)	
//	* 0 0 0 0 * 0 0 0 0 * 0 0 0 0 FPER: frame sync period = FPER + 1 CLKG
cycles (NA)
// ***PCR1_R = 0x000D***
//	* 0 NA
//	0 IDLEEN: McBSP remains active during idle
//	0 XIOEN: transmitter pins are set as serial port pins
//	0 RIOEN: receiver pins are set as serial port pins
//	* 0 FSXM: FSX input, driven by SPI master (***REQUIRED***)
//	0 FSRM: FSR input, driven by SPI master (NA; FSR internally
connected)	
//	0 CLKXM: CLKX input, driven by master; CLKR driven internally by CLKX
(***REQUIRED***)
//	0 CLKRM: CLKR input, driven by master (NA; CLKR intenally connected)
//	* 0 SCLKME: SRG clock derived from McBSP internal input clock (CLKX)
(***REQUIRED***)
//	0 CLKSTAT: CLKS status (NA; no CLKS)
//	0 DXSTAT: drive DX pin (NA; serial port mode)
//	0 DRSTAT: drive DR pin (NA; serial port mode)
//	* 1 FSXP: tx frame sync polarity = active low (***REQUIRED***)
//	1 FSRP: rx frame sync polarity = active low (NA???)
//	0 CLKXP: tx data on CLKX rising edge (***REQUIRED***)
//	1 CLKRP: rx data on CLKX rising edge (***REQUIRED***)

Thank you for reading!

Craig Neely

c...@centeye.com

______________________________
New Year Gift for Members of DSPRelated.com.  Details here.

hi,

You cannot use DLB mode and clock stop mode at the same time in a 
mcbsp.

regards,
Dileepan.
--- In c...@yahoogroups.com, "Prasad B C." <prasadbc@...> wrote:
>
> Hi,
> 
>    The best way to solve the problem is, with the same setting you 
enable
> DLB(Digital Loop Back Mode) and check out are you getting data back 
what you
> have sent. This procedure confirms McBSP is working.
> 
> Rgds
> -Prasad
> 
> -----Original Message-----
> From: c...@yahoogroups.com [mailto:c...@yahoogroups.com] On Behalf 
Of
> cneely@...
> Sent: Saturday, June 17, 2006 6:10 AM
> To: c...@yahoogroups.com
> Subject: [c55x] McBSP as an Interrupt-Driven SPI Slave
> 
> Hello!
> 
> I am trying to get McBSP1 on my C5509A to behave as an interrupt-
driven SPI
> slave device. I am experienced with this DSP (using it for 1.5 
years now),
> but this seemingly simple setup is stumping me. I would very much 
appreciate
> any help a DSP Related user could give me.
> 
> **********Goal (For Debugging)**********
> - On each frame transmitted by the master (FSX low and 8-bits 
clocked out),
> the DSP should transmit a preset value (0xAA chosen arbitrarily).
> - On each frame the DSP will check the value received from the 
master and
> compare it to an expected value (0x18 chosen arbitrarily). If the 
values
> match, an I/O line will change state (for debugging).
> 
> Simple, right?
> 
> **********Currently**********
> - My XRDY and RRDY interrupt handlers "fire" once each per frame. 
XRDY fires
> somewhere in the middle of the clocking sequence (I believe after 
the
> previously loaded DXR is transferred to DSR). RRDY fires after FSX 
returns to
> high (inactive).
> - The DSP transmits "junk" to the master each frame, but this junk 
is
> somewhat correlated to the value that the master sent. This means 
that for
> any given value I have the master send to the DSP, the DSP responds 
with a
> distinct "set" of junk what looks like a random order.
> 
> For example:
> Value Sent: 0xAA
> DSP transmits (not in order): 0x20, 0x40, 0x50, 0x54, 0x5F, 0x94
> Value Sent: 0x18
> DSP transmits: 0x00, 0x3F, 0x40, 0x80
> 
> - My test to check if the DSP's received value was 0x18 passes only
> occasionally, though I send it 0x18 each frame.
> 
> Interestingly, the test only seems to pass on frames when the DSP 
transmits
> 0x40 (in response to the master's 0x18).
> 
> **********Hardware Connection**********
> CLKX1 <--- SCK
> DX1 ---> MISO
> DR1 <--- MOSI
> FSX <--- /SS
> - SCK rate is 4 MHz. I've tried 250 kHz as well.
> - Data is to be sampled on rising edges of CLKX, shifts out next 
bit on
> falling edges.
> 
> **********Setup Procedure**********
> /* 
***************************************************************** */
> 	// initialize the chip support libraries
> 	CSL_init();
> 
> 	// configure PLL and set frequency
> 	PLL_config(&PLLStdConfig);
> 
> 	// temporarily disable all maskable interrupts
> 	OldINTM = IRQ_globalDisable();
> 
> 	// set IVPH/IVPD to start of interrupt vector table
> 	IRQ_setVecs((Uint32)(&VECSTART));
> /* 
***************************************************************** */
> 	// setup GPIO registers
> 	PCBSetup();
> 
> /* 
***************************************************************** */
> 	// open McBSP1 for communications and hold it in reset
> 	hMCBSP1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
> 
> 	// program the McBSP1 control registers
> 	MCBSP_config(hMCBSP1, &McBSP1ConfigStructure);
> 
> 	// get event IDs for interrupt setup
> 	Port1RXEventID = MCBSP_getRcvEventId(hMCBSP1);
> 	Port1TXEventID = MCBSP_getXmtEventId(hMCBSP1);
> 
> 	// insert SPI interrupts into the vector table
> 	IRQ_plug(Port1RXEventID, &SpiRxIsr);
> 	IRQ_plug(Port1TXEventID, &SpiTxIsr);
> 
> 	// enable interrupts
> 	IRQ_enable(Port1RXEventID);
> 	IRQ_enable(Port1TXEventID);
> 
> 	// set initial values
> 	DXR1_1_R = 0xAAAA;
> 	SpiTxVal = 0;
> 	SPITxBegin = 0;
> 
> 	// start SRG
> 	MCBSP_start(hMCBSP1, MCBSP_SRGR_START, 0x00AA);
> 
> 	// start transmitter and receiver
> 	MCBSP_start(hMCBSP1, MCBSP_XMIT_START | MCBSP_RCV_START, 
0x00AA);
> 
> 	// enable all maskable interrupts
> 	IRQ_globalEnable();
> 
> **********Interrupt Handlers**********
> //******************************************************************
***//
> interrupt void SpiTxIsr(void)
> //******************************************************************
***//
> {
> 	MCBSP_write16(hMCBSP1, 0xAAAA);
> }
> //******************************************************************
***//
> interrupt void SpiRxIsr(void)
> //******************************************************************
***//
> {
> 	SpiTxVal = MCBSP_read16(hMCBSP1);
> 
> 	if ((SpiTxVal & 0x00FF) == 0x0018)
> 	{
> 		SPITxBegin = !SPITxBegin;
> 
> 		if (SPITxBegin)
> 			AGPIODATA_R |= AGPIO_9;
> 		else
> 			AGPIODATA_R &= ~AGPIO_9;
> 	}
> }
> 
> **********Configuration Structure (With Notes)**********
> I've noted here what each bit should do, which bits are required 
according to
> the McBSP User Guide for SPI Slave mode, and which bits should be 
Not
> Applicable due to other settings.
> 
> // SPI Serial Port for External Communications (Interrupt-Driven 
Slave)
> MCBSP_Config 	McBSP1ConfigStructure = {
> 		0x1800,		// SPCR1
> 		0x0000,		// SPCR2
> 		0x0000,		// RCR1
> 		0x0000,		// RCR2
> 		0x0000,		// XCR1
> 		0x0000,		// XCR2
> 		0x0001,		// SRGR1
> 		0x2000,		// SRGR2
> 		0x0000,		// MCR1
> 		0x0000,		// MCR2
> 		0x000D,		// PCR
> 		0x0000,		// RCERA
> 		0x0000,		// RCERB
> 		0x0000,		// RCERC
> 		0x0000,		// RCERD
> 		0x0000,		// RCERE
> 		0x0000,		// RCERF
> 		0x0000,		// RCERG
> 		0x0000,		// RCERH
> 		0x0000,		// XCERA
> 		0x0000,		// XCERB
> 		0x0000,		// XCERC
> 		0x0000,		// XCERD
> 		0x0000,		// XCERE
> 		0x0000,		// XCERF
> 		0x0000,		// XCERG
> 		0x0000		// XCERH
> 		};
> // ***SPCR1_1_R = 0x1800***
> //	* 0 DLB: no digital loopback
> //	0 0 RJUST: right justify, unsigned data
> //	1 * 1 CLKSTP: clock stop mode, half-cycle delay 
(***REQUIRED***)
> //	0 0 0 NA
> //	* 0 DXENA: first-bit DX delay off
> //	0 NA
> //	0 0 RINTM: RINT on RRDY (0->1)
> //	* 0 RSYNCERR: rx frame sync error status
> //	0 RFULL: rx full error status
> //	0 RRDY: rx ready status	(DRR1 read to clear)
> //	0 RRST: hold rx in reset
> // ***SPCR2_1_R = 0x0000***
> //	* 0 0 0 0 * 0 0 NA
> //	0 FREE: module stops running during emulation break
> //	0 SOFT: hard stop duing emulation break
> //	* 0 FRST: hold frame sync logic in reset
> //	0 GRST: hold sample rate generator (SRG) in reset
> //	0 0 XINTM: XINT on XRDY (0->1)
> //	* 0 XYNCERR: tx frame sync error status
> //	0 XEMPTY: tx empty error status
> //	0 XRDY: tx ready status (DXR1 load to clear)
> //	0 XRST: hold tx in reset
> // ***RCR1_1_R = 0x0000***
> //	* 0 NA
> //	0 0 0 * 0 0 0 0 RFRLEN1: rx frame 1 length = 1 word 
(***REQUIRED***)
> //	* 0 0 0 RWDLEN1: rx word length = 8 bits (***REQUIRED (same as
> XWDLEN1)***)
> //	0 * 0 0 0 0 NA
> // ***RCR2_1_R = 0x0000***
> //	* 0 RPHASE: single phase frame (turns off phase 2) 
(***REQUIRED***)
> 
> //	0 0 0 * 0 0 0 0 RFRLEN2: rx frame 2 length = 1 word (NA)
> //	* 0 0 0 RWDLEN2: rx word length = 8 bits (NA)
> //	0 * 0 RCOMPAND: no companding, MSB first
> //	0 RFIG: FSR pulse causes RSR to be discarded; begin new rx
> //	0 0 RDATDLY: 0-bit delay between frame sync and reception
> (***REQUIRED***)
> // ***XCR1_1_R = 0x0000***
> //	* 0 NA
> //	0 0 0 * 0 0 0 0 XFRLEN1: tx frame 1 length = 1 word 
(***REQUIRED***)
> //	* 0 0 0 XWDLEN1: tx word length = 8 bits (***REQUIRED (same as
> RWDLEN1)***)
> //	0 * 0 0 0 0 NA
> // ***XCR2_1_R = 0x0000***
> //	* 0 XPHASE: single phase frame (turns off phase 2) 
(***REQUIRED***)
> 
> //	0 0 0 * 0 0 0 0 XFRLEN2: tx frame 2 length = 1 word (NA)
> //	* 0 0 0 XWDLEN2: tx word length = 8 bits (NA)
> //	0 * 0 XCOMPAND: no companding, MSB first
> //	0 XFIG: FSX pulse causes XSR to be discarded; begin new tx
> //	0 0 XDATDLY: 0-bit delay between frame sync and transmission
> (***REQUIRED***)
> // ***SRGR1_1_R = 0x0001***
> //	* 0 0 0 0 * 0 0 0 0 FWID: frame sync pulse width = 1 CLKG 
cycle	(NA;
> FS external)
> //	* 0 0 0 0 * 0 0 0 1 CLKGDV: McBSP internal input clock / 2 
for CLKG
> (***REQUIRED***)
> // ***SRGR2_1_R = 0x2000***
> //	* 0 GSYNC: no clock sync to CLKS or CLKR (NA; FSR internally
> connected)
> //	0 CLKSP: CLKS pin rising edge triggered (NA; no CLKS)
> //	1 CLKSM: input clock from McBSP internal input clock (CLKX)
> (***REQUIRED***)
> //	0 FSGM: FSX when DXR copied to XSR (NA; FSXM = 0)
> //	* 0 0 0 0 * 0 0 0 0 * 0 0 0 0 FPER: frame sync period = FPER 
+ 1 CLKG
> cycles (NA)
> // ***PCR1_R = 0x000D***
> //	* 0 NA
> //	0 IDLEEN: McBSP remains active during idle
> //	0 XIOEN: transmitter pins are set as serial port pins
> //	0 RIOEN: receiver pins are set as serial port pins
> //	* 0 FSXM: FSX input, driven by SPI master (***REQUIRED***)
> //	0 FSRM: FSR input, driven by SPI master (NA; FSR internally
> connected)
> //	0 CLKXM: CLKX input, driven by master; CLKR driven internally 
by CLKX
> (***REQUIRED***)
> //	0 CLKRM: CLKR input, driven by master (NA; CLKR intenally 
connected)
> //	* 0 SCLKME: SRG clock derived from McBSP internal input clock 
(CLKX)
> (***REQUIRED***)
> //	0 CLKSTAT: CLKS status (NA; no CLKS)
> //	0 DXSTAT: drive DX pin (NA; serial port mode)
> //	0 DRSTAT: drive DR pin (NA; serial port mode)
> //	* 1 FSXP: tx frame sync polarity = active low (***REQUIRED***)
> //	1 FSRP: rx frame sync polarity = active low (NA???)
> //	0 CLKXP: tx data on CLKX rising edge (***REQUIRED***)
> //	1 CLKRP: rx data on CLKX rising edge (***REQUIRED***)
> 
> Thank you for reading!
> 
> Craig Neely
> 
> cneely@...
>

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