Hi all,

I have a 5510 connected to an external device over the EMIF as 
asynchronous memory, and I want to DMA from internal RAM to this 
device.

I also want to run my CPU at full speed (200MHz), which gives a CPU 
cycle of 5ns.

However, the timing constraints when writing to my external device 
require me to configure a minimum hold period of 70ns before I can 
re-assert the write strobe.

Given that the WRHOLD field only allows up to 3 CPU clock cycles for 
the hold period, the only way I can meet my devices timing 
requirements is to drop my CPU down to ~40MHz.

Does anybody know of any clever ways around this ?

On other DSPs I have used it has been possible to run the equivalent 
of the EMIF at a different clock speed from that of the CPU. Is that 
true of the 5510 ?

Thanks in advance for any response.

Cheers,

Scottie

Scott-

> I have a 5510 connected to an external device over the EMIF as
> asynchronous memory, and I want to DMA from internal RAM to this
> device.
>
> I also want to run my CPU at full speed (200MHz), which gives a CPU
> cycle of 5ns.
>
> However, the timing constraints when writing to my external device
> require me to configure a minimum hold period of 70ns before I can
> re-assert the write strobe.
>
> Given that the WRHOLD field only allows up to 3 CPU clock cycles for
> the hold period, the only way I can meet my devices timing
> requirements is to drop my CPU down to ~40MHz.
>
> Does anybody know of any clever ways around this ?
>
> On other DSPs I have used it has been possible to run the equivalent
> of the EMIF at a different clock speed from that of the CPU. Is that
> true of the 5510 ?

I think it is possible using EMIF CLKIN signal, but I would recommend
deriving the 40 MHz externally from the same clock source you are using
for DSP clock input.  For example, provide 40 MHz ext, use PLL multiplier
of 5.

When CLKIN is not sychronized with the DSP clock, then I think you might
have some trouble.

-Jeff

hi Scottie,

1) You say there is a requirement of 70 ns before you
can re-assert the write strobe. Are you referring to
AWE as the write strobe? Looking at the c5510 data
sheet for asynchronous memory write timing with
respect to AWE,wont this 70 ns include the set up time
for the next write cycle? So am i correct in saying
that requirement is hold time of current write cycle+
setup time for next write cycle = 70 ns ?  

Still, even with 5ns cpu cycle time and max values for
setup and hold, it may be hard to match the timimg.
You can think of delaying some specific signals by
passing through external devices like latches/buffers
to match timing. 

2) Reducing the CPU clock is also an option. But if
the point 1 is true for you, then you need not reduce
it to as low as 40Mhz. 

3) The EMIF clock for asynchronous interface runs at
CPU clock in 5510. The clock rates for EMIF can be
changed only for synchronous memories in 5510.

regards,
Dileepan.
--- smiffoz <s...@yahoo.co.uk> wrote:

> Hi all,
> 
> I have a 5510 connected to an external device over
> the EMIF as 
> asynchronous memory, and I want to DMA from internal
> RAM to this 
> device.
> 
> I also want to run my CPU at full speed (200MHz),
> which gives a CPU 
> cycle of 5ns.
> 
> However, the timing constraints when writing to my
> external device 
> require me to configure a minimum hold period of
> 70ns before I can 
> re-assert the write strobe.
> 
> Given that the WRHOLD field only allows up to 3 CPU
> clock cycles for 
> the hold period, the only way I can meet my devices
> timing 
> requirements is to drop my CPU down to ~40MHz.
> 
> Does anybody know of any clever ways around this ?
> 
> On other DSPs I have used it has been possible to
> run the equivalent 
> of the EMIF at a different clock speed from that of
> the CPU. Is that 
> true of the 5510 ?
> 
> Thanks in advance for any response.
> 
> Cheers,
> 
> Scottie
__________________________________________________

Hi Scottie,=20

on the c5503 you can change the emif clock. I think it is the same, but tak=
e a=20
look to be sure. Anyway you can use the handshake signal (async ready) to=20
longer the access time-=20

Michael=20
Am Freitag, 16. Juni 2006 16:11 schrieben Sie:
> Hi all,
>
> I have a 5510 connected to an external device over the EMIF as
> asynchronous memory, and I want to DMA from internal RAM to this
> device.
>
> I also want to run my CPU at full speed (200MHz), which gives a CPU
> cycle of 5ns.
>
> However, the timing constraints when writing to my external device
> require me to configure a minimum hold period of 70ns before I can
> re-assert the write strobe.
>
> Given that the WRHOLD field only allows up to 3 CPU clock cycles for
> the hold period, the only way I can meet my devices timing
> requirements is to drop my CPU down to ~40MHz.
>
> Does anybody know of any clever ways around this ?
>
> On other DSPs I have used it has been possible to run the equivalent
> of the EMIF at a different clock speed from that of the CPU. Is that
> true of the 5510 ?
>
> Thanks in advance for any response.
>
> Cheers,
>
> Scottie
>

--=20
____________________________________________________
Dr.-Ing. Michael Schuster
Gesch=E4ftsf=FChrer

Enertex Bayern GmbH
Innovative Systeml=F6sungen der Energie- und Elektrotechnik
www.enertex.de=20=20=20=20=20=20=20=20=20=20=20

Erlachstra=DFe 13           91301 Forchheim
Tel: ++49-9191-974 637 Fax: ++49-9191-974 687  Mob:0175 5151913

=20

=20