Dear all, I want to implement a noise canceler to remove artifacts from ECG signal using TI DSP. Please suggest me which DSP is more suitable...

Dear all, I want to implement a noise canceler to remove artifacts from ECG signal using TI DSP. Please suggest me which DSP is more suitable for this application. I heard that using MATLAB real time workshop, we can directly give MATLAB code to DSP with out converting to C. Please elaborate this. In our MATLAB simulations the ECG data is loaded using load command, in DSP implementation ...

Hi!, I am trying to use the new software ccsv4 with old examples that use the edma module but my code is not linked, i do not why this happens, in...

Hi!, I am trying to use the new software ccsv4 with old examples that use the edma module but my code is not linked, i do not why this happens, in ccsv3.1 the program works fine but in the new software it does not work. Could any help me? The code that i use is the following: #include #include #include "sine.h" #include "edma.h" /* * ======== Declarations ====

The function I am using is from Texas Instruments Little Endian DSPLIB : void DSP_fft(const short *w, int nsamp, short *x, short *y). Twiddle...

The function I am using is from Texas Instruments Little Endian DSPLIB : void DSP_fft(const short *w, int nsamp, short *x, short *y). Twiddle factors are calculated with tw_fft16x16.c code. x,y and w are double-word aligned as requested. When I use 32-point FFT for all zero input signal, as output I get this: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1500 6553 29596 -18457 0 0...

Hello folks, I'm using the TMS320C6424 in a system designed for a railway application, my FW must include a DSP-self test, executed periodically...

Hello folks, I'm using the TMS320C6424 in a system designed for a railway application, my FW must include a DSP-self test, executed periodically in order to check that everything is working as expected. Do you know the source code or an example of C6424 self test? I need something similar to spra838a ("TMS320C6416 Power-On Self Test") but suited to C6424. Thanks in advance Gio _____________...

All- I wanted to add that I'm still concerned about possible JTAG + USB "background communication", a theory that would fit the constant...

All- I wanted to add that I'm still concerned about possible JTAG + USB "background communication", a theory that would fit the constant slow-down factor, assuming that CCS4 talks with the chip on a periodic basis. I didn't get any reply to my question about "where is Free Run" in CCS4. A couple of other notes: 1) Andrey's x, h, and y data are aligned to multiple of 8 (we can see it in...

The cycle count of "NH*NR/8+22" assumes only CPU cycles and does not and cannout account for memory sub-system effects. When you work on such...

The cycle count of "NH*NR/8+22" assumes only CPU cycles and does not and cannout account for memory sub-system effects. When you work on such large arrays, you see additional stall cycles due to memory hierarchy. Your results will be the best if you can fit in L2 memory of the processor the section you refer to as DMC_SRAM. The next best set of results will be when you use combination of DMC_...

~1 = 0xfffffffe -1 = 0xffffffff

~1 = 0xfffffffe -1 = 0xffffffff

All- We have been unable to find a combination of C source code and compiler options that will cause the TI C64x+ compiler to generate a...

All- We have been unable to find a combination of C source code and compiler options that will cause the TI C64x+ compiler to generate a DDOTPL2 (multiply-and-accumulate) instruction. I find that surprising since super-efficient MAC has been a TI staple for many years. Does anyone (in particular TI persons monitoring this group) know whether there is a way? Also, is there an app note a...

All- Forgot to mention: we read the PLL1 multiplier control register and verified that BIOS had set a multiplier of 28 (25 MHz onboard osc x...

All- Forgot to mention: we read the PLL1 multiplier control register and verified that BIOS had set a multiplier of 28 (25 MHz onboard osc x 28 = 700 MHz). The divider is not enabled. -Jeff --------------- Original Message -------------- Subject: BIOS profiling not matching cycle counts From: "Jeff Brower" Date: Fri, October 8, 2010 9:35 pm To: c...