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Dear DSPers, I need to design a communication scheme for C6415 to be able to communicate with a host processor. I am wondering someone could explain to me how to do this for C6415 ? Host -------- (1) put information to DSP internal memmory. (2) to generate an interrupt to DSP via PCI port ? Thank you very much for your information and help. Sincerely, Jay Huang

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Jay, If the 6415 uses the same bridge as the 6205 be careful of a potential race condition. The memory cycle is fifo'ed. The register cycle (to cause the dsp interrupt), is not. jrc John R Campbell March Networks Corporation Tower B, Suite 330, 555 Legget Drive Kanata, Ontario K2K 2X3 T (613) 591-8228 Ext 5809 F (613) 591-3113

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Jay, Basically you need write a host driver to do that. You can access your DSP target memeory through the Base Addess 0 space. Also you can use DMA to let C6415 read/write host memory as a PCI bus master. I would sugguest you use DMA whenever possible because the host access to DSP may not write to the target correctly when other PCI activiy is in the bus due to the problem in c6415's PCI interface. In order to interrupt the DSP from host, just write the DSPINT bit in HDCR regiseter through the Base Address 2 memory. Writing this bit will cause the HOSTSW interrupt if it is enabled in the PCI interrupt enable register (PCIIEN). Regards, William --- Jay Huang <> wrote: > Dear DSPers, > > I need to design a communication scheme for C6415 to > be able to communicate with a host processor. I am > wondering someone could explain to me how to do this > for C6415 ? > > Host > -------- > (1) put information to DSP internal memmory. > (2) to generate an interrupt to DSP via PCI port ? > > Thank you very much for your information and help. > > Sincerely, > > Jay Huang > > _____________________________________ __________________________________________________

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Hello, > read/write host memory as a PCI bus master. I would > sugguest you use DMA whenever possible because the > host access to DSP may not write to the target > correctly when other PCI activiy is in the bus due to > the problem in c6415's PCI interface. What do you mean with "due to the problem in c6415's PCI interface" ? Thanks J-F

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Hello, Please find below the answer that I just got from TI, to be included in next release of the errata file. J-F >> What do you mean with "due to the problem in c6415's PCI >> interface" ? > > Hello, > > There is a silicon bug in C6415 PCI interface. TI > is actually working on it. I did a street test to > write/read the DSP memory from host using DSP as PCI > target, the data read back are not exactly same as > wrote sometimes. The error rate is more than 1% if > there is other PCI activity on the bus meanwhile. > > Regards, > William -------------- ANSWER FROM TI -------------- 3 - Silicon Revision 1.03 Known Design Exceptions to Functional Specifications and Usage Notes : 3.1 Usage Notes for Silicon Revision 1.03. PCI: Bursts of 11 Words Sometimes Corrupt Data On silicon revision 1.03 and earlier, when doing a PCI burst slave write to the DSP that is 11 words long, the data may get corrupted. When the data corruption occurs, the eleventh word of the burst ends up in memory where the first word goes, and the memory location where the eleventh word should have gone is left untouched. The data corruption issue has only been observed in systems where there are several devices on the PCI bus (for example, a PC).

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