Technical discussions about the TI C6000 DSPs (including the c62x, c64x and c67x DSPs).
be carefull of getting into cache coherency problems!!! you might get rando=
m data in L2!
Chekib
----- Message d'origine ----
De : "s...@hotmail.com" <s...@hotmail.com>
=C3=80 : c...@yahoogroups.com
Envoy=C3=A9 le : Mercredi, 12 Mars 2008, 22h35mn 16s
Objet : [c6x] Ext Memory access without EDMA
Hi everyone,
=20
Is it possible to access external memory without using EDMA. I would like =
to pass a buffer pointer located in external memory to a function call with=
out configuring EDMA. The DSP i am using is C6713. I would configure whole =
L2 as SRAM (256K) i.e., no L2 cache.
=20
Any comment will be appreciated.
=20
Thanks
=20
Sankar Barua
=20
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Tr=
anscoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm64=
67
=20
The great thing about disabling the L2 cache is that you don't have to
worry about cache interactions. If you have disabled the cache, you've
got access to 256k of internal ram to work with, and can directly access
whatever external ram you have available wherever it is addressed.
I'm working with two boards, one has 1Mbyte of external SBSRAM located
at 0x80000000 and the other has 32Mbytes of SDRAM located at the same
starting position. Since my program is currently written to be able to
work on both boards using cache, I've got my linker config set up as
follows. I declare the cache here, just so that I won't forget that the
ram is used. My system boots a bios that takes the first 0x1300 bytes of
ram.
MEMORY
{
L2RAM : org = 0x00001300, len = 0x0002ED00
CACHE : org = 0x00030000, len = 0x00010000
SRAM : org = 0x80000000, len = 0x00100000 /* First Megabyte of
ram exists on both old and new boards */
SRAMEX : org = 0x80100000, len = 0x01F00000 /* new boards have
twice the RAM that the original boards had */
/* V1 Board Samsung K6X8016T3B-TF55 512*1024*16 bits */
/* V2 Board Samsung K4S561632E-TI75 16*1024*1024*16 bits */
}
Then my sections portion of the linker config allocates things into the
memory locations that I want to use. You can see how I'm splitting the
.text and .far sections into both internal and external ram as the
linker wants to. (I've actually got more sections defined, as I have
code that I explicitly want in internal and external memory. I have
those declared initially and just let the linker take care of what's
left. It is really amazing how slow external ram is compared to the L2
Ram, as well as how much improvement the cache can provide.
The comments that I've included about each of the sections were copied
directly from TI documentation. I include them for reference purposes only.
SECTIONS
{
.stack > L2RAM
.sysmem > L2RAM /* The .sysmem section reserves space for
dynamic memory allocation. The reserved space is used by the malloc,
calloc, and realloc functions. If a C/C++ program does not use these
functions, the compiler does not create the .sysmem section. */
.cio > L2RAM
.switch > L2RAM /* The .switch section contains tables for
large switch statements. */
.data > L2RAM /* .data is not used by the C compiler */
.bss > L2RAM /* The .bss section reserves space for global and
static variables. When you specify the -c linker option, at program
startup, the C/C++ boot routine copies data out of the .cinit section
(which can be in ROM) it in the .bss section. The compiler defines the
global symbol $bss and assigns $bss the value of the starting address of
the .bss section. */
.text >> L2RAM | SRAM /* Use the >> operator to indicate that an
output section can be split, if necessary, into the specified memory
ranges. */
.far >> L2RAM | SRAM /* The .far section reserves space for
global and static variables that are declared far. */
.cinit > SRAM /* The .cinit section contains tables for
initializing variables and constants. I believe that this is only the
values that are used to initialize things at startup, and so are not
needed during runtime. */
.const > SRAM /* The .const section contains string literals,
floating-point constants, and data defined with the C/C++ qualifier
const (provided the constant is not also defined as volatile). */
.pinit > SRAM /* Table of Global Object Constructors. See
below for full description */
}
/* .pinit Description: Global C++ variables having constructors and
destructors require their constructors to be called during program
initialization and their destructors to be called during program
termination. The C/C++ compiler produces a table of constructors to be
called at startup. The table is contained in a named section called
.pinit. The constructors are invoked in the order that they occur in the
table. Global constructors are called after initialization of other
global variables and before main( ) is called. Global destructors are
invoked during exit( ), similar to functions registered through atexit(
). */
chekib nouira wrote:
> be carefull of getting into cache coherency problems!!! you might get random data in L2!
>
> Chekib
> ----- Message d'origine ----
> De : "s...@hotmail.com" <s...@hotmail.com>
> À : c...@yahoogroups.com
> Envoyé le : Mercredi, 12 Mars 2008, 22h35mn 16s
> Objet : [c6x] Ext Memory access without EDMA
>
> Hi everyone,
>
> Is it possible to access external memory without using EDMA. I would like to pass a
buffer pointer located in external memory to a function call without configuring EDMA. The DSP
i am using is C6713. I would configure whole L2 as SRAM (256K) i.e., no L2 cache.
>
> Any comment will be appreciated.
>
> Thanks
>
> Sankar Barua
>
>
>
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467
Of course it is possible, it will just be a lot slower...around 10 times!
Thank you folks for reply. I am not using L2 Cache for two reasons: 1. I will be running shortage of RAM. 2. Most importantly, i am reading a block of data from Ext RAM only once. I read them into internal memory and process it from internal memory. At that point i don't care about the data in Ext memory. I keep hearing that i will lose speed if i don't use cache. My rational is that as long as i read the data only once it does not matter wheather you use cache or not speed will be the same. If you refer the same data more than once then cache hit helps to speed up. Am I right. Please comments: Sankar be carefull of getting into cache coherency problems!!! you might get rando= >m data in L2! > >Chekib >----- Message d'origine ---- >De : "s...@hotmail.com" >=C3=80 : c...@yahoogroups.com >Envoy=C3=A9 le : Mercredi, 12 Mars 2008, 22h35mn 16s >Objet : [c6x] Ext Memory access without EDMA > > Hi everyone, >=20 > Is it possible to access external memory without using EDMA. I would like = >to pass a buffer pointer located in external memory to a function call with= >out configuring EDMA. The DSP i am using is C6713. I would configure whole = >L2 as SRAM (256K) i.e., no L2 cache. >=20 > Any comment will be appreciated. >=20 > Thanks >=20 > Sankar Barua >=20 >Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Tr= >anscoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm64= >67 > >=20 > ------------------------------------ Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Sankar, On Thu, Mar 13, 2008 at 12:57 PM, <s...@hotmail.com> wrote: > Thank you folks for reply. I am not using L2 Cache for two reasons: > > 1. I will be running shortage of RAM. > 2. Most importantly, i am reading a block of data from Ext RAM only once. I > read them into internal memory and process it from internal memory. At that > point i don't care about the data in Ext memory. > > I keep hearing that i will lose speed if i don't use cache. There is not a single answer to "should I use cache". One needs to understand the application, DSP, and the DMA/cache/memory subsystem to make the best decision. Sometimes experiments are required. Many [most??] uses of DSPs involve a number of loops/iterations that get significant performance gains from using cache. It is not always the answer. > My rational is > that as long as i read the data only once it does not matter wheather you > use cache or not speed will be the same. If you refer the same data more > than once then cache hit helps to speed up. Am I right. Please comments: You are correct. "Single access stuff" gains no benefit from using cache. mikedunn > > Sankar > > be carefull of getting into cache coherency problems!!! you might get > rando= > > >m data in L2! > > > >Chekib > >----- Message d'origine ---- > >De : "s...@hotmail.com" > >=C3=80 : c...@yahoogroups.com > >Envoy=C3=A9 le : Mercredi, 12 Mars 2008, 22h35mn 16s > > >Objet : [c6x] Ext Memory access without EDMA > > > > Hi everyone, > >=20 > > > Is it possible to access external memory without using EDMA. I would like > = > >to pass a buffer pointer located in external memory to a function call > with= > > >out configuring EDMA. The DSP i am using is C6713. I would configure whole > = > >L2 as SRAM (256K) i.e., no L2 cache. > >=20 > > > Any comment will be appreciated. > >=20 > > Thanks > >=20 > > Sankar Barua > >=20 > >Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video > Tr= > >anscoding Solution for Commercial & Consumer End Equipment: > www.ti.com/dm64= > >67 > > > >=20 > > > -- www.dsprelated.com/blogs-1/nf/Mike_Dunn.php ------------------------------------ Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467