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Dear All,

I am trying to implement QDMA in a video codec algorithm in DM6446 
simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am 
updating several memory mapped registers like QEESR like following,

funct1()
{
volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 
0x108c);

*QEESR = desired_value;
}

When I am returning back to the callee the address (0x1c0108c) is 
reverted back to 0x0.

This is happening for IESR register also. So I am not able get the 
correct bit set in IER, in turn the IPR bit corresponds to the 
appropriate channel remains 0 instead of 1. And so EDMA3CC not 
generating the interrupt.

Please help me resolving the issue.

Thanks,

Nilanjan

------------------------------------

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Nilanjan,

What is the value of 'desired_value'?  hopefully, not '0'.

this function is not returning anything, so is the function that is checking the value also
containing the line:
"volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 0x108c);"

I'm not familiar with the specific register at (0x1c00000 + 0x108c).
is it perhaps a write only register?

R. Williams
---------- Original Message -----------
From: Nilanjan Goswami <n...@cal.interrasystems.com>
To: c6x <c...@yahoogroups.com>
Sent: Tue, 08 Apr 2008 15:59:04 +0530
Subject: [c6x] memory mapped QDMA issue in DM6446 simulator

> Dear All,
> 
> I am trying to implement QDMA in a video codec algorithm in DM6446 
> simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am 
> updating several memory mapped registers like QEESR like following,
> 
> funct1()
> {
> volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 
> 0x108c);
> 
> *QEESR = desired_value;
> }
> 
> When I am returning back to the callee the address (0x1c0108c) is 
> reverted back to 0x0.
> 
> This is happening for IESR register also. So I am not able get the 
> correct bit set in IER, in turn the IPR bit corresponds to the 
> appropriate channel remains 0 instead of 1. And so EDMA3CC not 
> generating the interrupt.
> 
> Please help me resolving the issue.
> 
> Thanks,
> 
> Nilanjan
------- End of Original Message -------
------------------------------------

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Richard,

QEESR (queue event enable set register) value is writable and its value 
is non zero. This register is the only way to enable all the four 
channels. To avoid the problem of read modify, write separate set and 
clear register are provided for enabling the QDMA channel. The function 
where the line of code exist is a QDMA channel open routine. In the 
function it takes an array of PaRAM and array of Transfer completion 
code need to be used by the QDMA channels. QEESR is memory mapped at 
0x1c0108c.

The open routine is modifying the value at 0x1c0108c. But when it is 
comming out of the routine the value again gets modified to 0. SO the 
desired effect of QEESR is not occurring. Moreover, the same thing is 
true for IESR(interrupt enable set register), IER (interrupt enable 
register) registers also.

Please help.

Thanks,
Nilanjan

Richard Williams wrote:
>
> Nilanjan,
>
> What is the value of 'desired_value'? hopefully, not '0'.
>
> this function is not returning anything, so is the function that is 
> checking the value also
> containing the line:
> "volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 
> 0x108c);"
>
> I'm not familiar with the specific register at (0x1c00000 + 0x108c).
> is it perhaps a write only register?
>
> R. Williams
>
> ---------- Original Message -----------
> From: Nilanjan Goswami <n...@cal.interrasystems.com 
> <mailto:nilanjan%40cal.interrasystems.com>>
> To: c6x <c...@yahoogroups.com <mailto:c6x%40yahoogroups.com>>
> Sent: Tue, 08 Apr 2008 15:59:04 +0530
> Subject: [c6x] memory mapped QDMA issue in DM6446 simulator
>
> > Dear All,
> >
> > I am trying to implement QDMA in a video codec algorithm in DM6446
> > simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am
> > updating several memory mapped registers like QEESR like following,
> >
> > funct1()
> > {
> > volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 +
> > 0x108c);
> >
> > *QEESR = desired_value;
> > }
> >
> > When I am returning back to the callee the address (0x1c0108c) is
> > reverted back to 0x0.
> >
> > This is happening for IESR register also. So I am not able get the
> > correct bit set in IER, in turn the IPR bit corresponds to the
> > appropriate channel remains 0 instead of 1. And so EDMA3CC not
> > generating the interrupt.
> >
> > Please help me resolving the issue.
> >
> > Thanks,
> >
> > Nilanjan
> ------- End of Original Message -------
>
>  

------------------------------------

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for Commercial & Consumer End Equipment: www.ti.com/dm6467

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On Wed, Apr 9, 2008 at 12:37 AM, Nilanjan Goswami
<n...@cal.interrasystems.com> wrote:
> Richard,
>
>  QEESR (queue event enable set register) value is writable and its value
>  is non zero. This register is the only way to enable all the four
>  channels. To avoid the problem of read modify, write separate set and
>  clear register are provided for enabling the QDMA channel. The function
>  where the line of code exist is a QDMA channel open routine. In the
>  function it takes an array of PaRAM and array of Transfer completion
>  code need to be used by the QDMA channels. QEESR is memory mapped at
>  0x1c0108c.
>
>  The open routine is modifying the value at 0x1c0108c. But when it is
>  comming out of the routine the value again gets modified to 0. SO the
>  desired effect of QEESR is not occurring. Moreover, the same thing is
>  true for IESR(interrupt enable set register), IER (interrupt enable
>  register) registers also.
>
>  Please help.
>
>  Thanks,
>  Nilanjan
>
>  Richard Williams wrote:
>  >
>  > Nilanjan,
>  >
>  > What is the value of 'desired_value'? hopefully, not '0'.
>  >
>  > this function is not returning anything, so is the function that is
>  > checking the value also
>  > containing the line:
>  > "volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 +
>  > 0x108c);"
>  >
>  > I'm not familiar with the specific register at (0x1c00000 + 0x108c).
>  > is it perhaps a write only register?
>  >
>  > R. Williams
>  >
>  > ---------- Original Message -----------
>  > From: Nilanjan Goswami <n...@cal.interrasystems.com
>  > <mailto:nilanjan%40cal.interrasystems.com>>
>  > To: c6x <c...@yahoogroups.com <mailto:c6x%40yahoogroups.com>>
>  > Sent: Tue, 08 Apr 2008 15:59:04 +0530
>  > Subject: [c6x] memory mapped QDMA issue in DM6446 simulator
>  >
>  > > Dear All,
>  > >
>  > > I am trying to implement QDMA in a video codec algorithm in DM6446
>  > > simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am
>  > > updating several memory mapped registers like QEESR like following,
>  > >
>  > > funct1()
>  > > {
>  > > volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 +
>  > > 0x108c);
>  > >
>  > > *QEESR = desired_value;
>  > > }
>  > >
>  > > When I am returning back to the callee the address (0x1c0108c) is
>  > > reverted back to 0x0.
>  > >
>  > > This is happening for IESR register also. So I am not able get the
>  > > correct bit set in IER, in turn the IPR bit corresponds to the
>  > > appropriate channel remains 0 instead of 1. And so EDMA3CC not
>  > > generating the interrupt.

Are you assigning ownership to your processor??

QRAEn: One register exists for every region. The number of bits in
each register matches the number
of QDMA channels (8 QDMA channels).These registers need to be
programmed to assign ownership
of QDMA channels to the respective region. To enable a channel in a
shadow region, using shadow
region 0 QEER, writing into QEESR will not have the desired effect if
the respective bit in QRAE is not
set.

mikedunn
>  > >
>  > > Please help me resolving the issue.
>  > >
>  > > Thanks,
>  > >
>  > > Nilanjan
>  > ------- End of Original Message -------
>  >
>  >  

-- 
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php

------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

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Nilan,

The register QEESR is a 'set' register, and is writable, not readable

When is the register readable for the value written? - never
instead, per http://focus.ti.com/lit/ug/spru987a/spru987a.pdf
the register QEER must be read to see the current state.

The QEER register value will be a combination of:
system reset value = 0
QEESR - sets bits in QEER
QEECR - clears bits in QEER

---------- Original Message -----------
From: Nilanjan Goswami <n...@cal.interrasystems.com>
To: Richard Williams <r...@lewiscounty.com>
Cc: c6x <c...@yahoogroups.com>
Sent: Wed, 09 Apr 2008 11:07:49 +0530
Subject: Re: [SPAM] {Disarmed} Re: [c6x] memory mapped QDMA issue in DM6446 simulator

> Richard,
> 
> QEESR (queue event enable set register) value is writable and its value 
> is non zero. This register is the only way to enable all the four 
> channels. To avoid the problem of read modify, write separate set and 
> clear register are provided for enabling the QDMA channel. The function 
> where the line of code exist is a QDMA channel open routine. In the 
> function it takes an array of PaRAM and array of Transfer completion 
> code need to be used by the QDMA channels. QEESR is memory mapped at 
> 0x1c0108c.
> 
> The open routine is modifying the value at 0x1c0108c. But when it is 
> comming out of the routine the value again gets modified to 0. SO the 
> desired effect of QEESR is not occurring. Moreover, the same thing is 
> true for IESR(interrupt enable set register), IER (interrupt enable 
> register) registers also.
> 
> Please help.
> 
> Thanks,
> Nilanjan
> 
> Richard Williams wrote:
> >
> > Nilanjan,
> >
> > What is the value of 'desired_value'? hopefully, not '0'.
> >
> > this function is not returning anything, so is the function that is 
> > checking the value also
> > containing the line:
> > "volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 
> > 0x108c);"
> >
> > I'm not familiar with the specific register at (0x1c00000 + 0x108c).
> > is it perhaps a write only register?
> >
> > R. Williams
> >
> > ---------- Original Message -----------
> > From: Nilanjan Goswami <n...@cal.interrasystems.com 
> > <mailto:nilanjan%40cal.interrasystems.com>>
> > To: c6x <c...@yahoogroups.com <mailto:c6x%40yahoogroups.com>>
> > Sent: Tue, 08 Apr 2008 15:59:04 +0530
> > Subject: [c6x] memory mapped QDMA issue in DM6446 simulator
> >
> > > Dear All,
> > >
> > > I am trying to implement QDMA in a video codec algorithm in DM6446
> > > simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am
> > > updating several memory mapped registers like QEESR like following,
> > >
> > > funct1()
> > > {
> > > volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 +
> > > 0x108c);
> > >
> > > *QEESR = desired_value;
> > > }
> > >
> > > When I am returning back to the callee the address (0x1c0108c) is
> > > reverted back to 0x0.
> > >
> > > This is happening for IESR register also. So I am not able get the
> > > correct bit set in IER, in turn the IPR bit corresponds to the
> > > appropriate channel remains 0 instead of 1. And so EDMA3CC not
> > > generating the interrupt.
> > >
> > > Please help me resolving the issue.
> > >
> > > Thanks,
> > >
> > > Nilanjan
> > ------- End of Original Message -------
> >
> >
------- End of Original Message -------
------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )

@ All,

I have gone through the EDMA related sprue. I am not able to understand 
the difference EDMA global region and Shadow region differences? In the 
code its using QREA mapped to 0x1c00380. So if I set QREA as 0xFF then 
will I be able to restrict the global region or shadow region 0. The 
CCS3.3 simulator of DM6446 does not shows ARM9 in the set up. So I am 
worried whether my code is trying to use ARm9 as EDMA master. If yes, 
then how I can transfer it to DSP. How to enble device interupt 
controller in this case so that CPU can understand the EDMA interrupt.

If any one of you have time then please explain me the whole process in 
brief, or send me some ppt which has brief and lucid description of EDMA3 .

@Mike
Thank you very much for your help.

@Robert
Thank you very much for your help.
Thanking you all,
Nilanjan
Richard Williams wrote:
> Nilan,
>
> The register QEESR is a 'set' register, and is writable, not readable
>
> When is the register readable for the value written? - never
> instead, per http://focus.ti.com/lit/ug/spru987a/spru987a.pdf
> the register QEER must be read to see the current state.
>
> The QEER register value will be a combination of:
> system reset value = 0
> QEESR - sets bits in QEER
> QEECR - clears bits in QEER
> ---------- Original Message -----------
> From: Nilanjan Goswami <n...@cal.interrasystems.com>
> To: Richard Williams <r...@lewiscounty.com>
> Cc: c6x <c...@yahoogroups.com>
> Sent: Wed, 09 Apr 2008 11:07:49 +0530
> Subject: Re: [SPAM] {Disarmed} Re: [c6x] memory mapped QDMA issue in DM6446 simulator
>
>   
>> Richard,
>>
>> QEESR (queue event enable set register) value is writable and its value 
>> is non zero. This register is the only way to enable all the four 
>> channels. To avoid the problem of read modify, write separate set and 
>> clear register are provided for enabling the QDMA channel. The function 
>> where the line of code exist is a QDMA channel open routine. In the 
>> function it takes an array of PaRAM and array of Transfer completion 
>> code need to be used by the QDMA channels. QEESR is memory mapped at 
>> 0x1c0108c.
>>
>> The open routine is modifying the value at 0x1c0108c. But when it is 
>> comming out of the routine the value again gets modified to 0. SO the 
>> desired effect of QEESR is not occurring. Moreover, the same thing is 
>> true for IESR(interrupt enable set register), IER (interrupt enable 
>> register) registers also.
>>
>> Please help.
>>
>> Thanks,
>> Nilanjan
>>
>> Richard Williams wrote:
>>     
>>> Nilanjan,
>>>
>>> What is the value of 'desired_value'? hopefully, not '0'.
>>>
>>> this function is not returning anything, so is the function that is 
>>> checking the value also
>>> containing the line:
>>> "volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 + 
>>> 0x108c);"
>>>
>>> I'm not familiar with the specific register at (0x1c00000 + 0x108c).
>>> is it perhaps a write only register?
>>>
>>> R. Williams
>>>
>>> ---------- Original Message -----------
>>> From: Nilanjan Goswami <n...@cal.interrasystems.com 
>>> <mailto:nilanjan%40cal.interrasystems.com>>
>>> To: c6x <c...@yahoogroups.com <mailto:c6x%40yahoogroups.com>>
>>> Sent: Tue, 08 Apr 2008 15:59:04 +0530
>>> Subject: [c6x] memory mapped QDMA issue in DM6446 simulator
>>>
>>>       
>>>> Dear All,
>>>>
>>>> I am trying to implement QDMA in a video codec algorithm in DM6446
>>>> simulator (CCS 3.3). I am using QDMA _BASE address as 0x1c00000. I am
>>>> updating several memory mapped registers like QEESR like following,
>>>>
>>>> funct1()
>>>> {
>>>> volatile unsigned int *QEESR = (volatile unsigned int *)(0x1c00000 +
>>>> 0x108c);
>>>>
>>>> *QEESR = desired_value;
>>>> }
>>>>
>>>> When I am returning back to the callee the address (0x1c0108c) is
>>>> reverted back to 0x0.
>>>>
>>>> This is happening for IESR register also. So I am not able get the
>>>> correct bit set in IER, in turn the IPR bit corresponds to the
>>>> appropriate channel remains 0 instead of 1. And so EDMA3CC not
>>>> generating the interrupt.
>>>>
>>>> Please help me resolving the issue.
>>>>
>>>> Thanks,
>>>>
>>>> Nilanjan
>>>>         
>>> ------- End of Original Message -------
>>>
>>>
>>>       
> ------- End of Original Message -------
>   

------------------------------------

Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

(You need to be a member of c6x -- send a blank email to c6x-subscribe@yahoogroups.com )