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hi everyone, I need to have same suggestion about a tranfer from the Emif to the internal data Ram througt a DMA channel. Actually, I have to tranfer a little extern FIFO of samples connected to the Emif bus interface into the on-chip data memory of the 6201 DSP, after that I'm going to perform a digital filtering. Since the input transfer buffer (FIFO) is narrow (deep only six elements), and I want that the CPU operate on a more larger buffer of samples, I need to put the input samples into a countiguous buffer before precessing them (I think a circular buffer would be too small !!). I' ve immediately thought about the burst tranfer mode of a DMA channel with the option of auto initialization mode; the truth of the matter is that I won't use the CPU to supply the changed reload values every block tranfer . Does anyone know if it's possible to configure the tranfer DMA that does it whitout the intervention of the CPU ! At least, how do I manage the data memory so that ther's no contention between the CPU and DMA. Thanks!

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Flavio Plos schrieb: > hi everyone, > > I need to have same suggestion about a tranfer from the Emif to the internal data Ram througt a DMA channel. > Actually, I have to tranfer a little extern FIFO of samples connected to the Emif bus interface into the on-chip > data memory of the 6201 DSP, after that I'm going to perform a digital filtering. > Since the input transfer buffer (FIFO) is narrow (deep only six elements), and I want that the CPU operate on > a more larger buffer of samples, I need to put the input samples into a countiguous buffer before precessing them > (I think a circular buffer would be too small !!). I' ve immediately thought about the burst tranfer mode of a DMA > channel with the option of auto initialization mode; the truth of the matter is that I won't use the CPU to supply the > changed reload values every block tranfer . > Does anyone know if it's possible to configure the tranfer DMA that does it whitout the intervention of the CPU ! > At least, how do I manage the data memory so that ther's no contention between the CPU and DMA. > > Thanks! to avoid contention between CPU and DMA, let the DMA issue an interrupt when it completes the frame i.e. after 6 elements. in the ISR, you can process the data or set a control flag for the application. alternatively, the CPU could poll for the DMA transfer complete flag (somewhere in the DMA control register). for transferring multiple frames, you can re-program reload registers before the next transfer is kickstarted or even while the transfer is running (as long as reload register access is finished before DMA re-uses them). the C6x1x EDMA features automatic linking of reload parameter sets such that the EDMA re-programs itself whithout CPU intervention. on C6x0x you can use the 2 reloads alternating and have to live with an ISR: refer to SPRU190 for more information on C6x DMA. Rgds. Phil -- Dipl.-Inf. Phil Alder - Field Application Engineer ------------------------------------------------------------------ DSPecialists GmbH Rotherstr. 22 10245 Berlin, Germany http://www.DSPecialists.de ------------------------------------------------------------------ DSPecialists - Making the impossible work!

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