AD535 | BIOS | Booting | Bootloader | C621 | C6211 | C6415 | C671 | C6711 | C6711DSK | C6713 | CCS | Chassaing | COFF | DAT | DM64 | DM642 | DMA | DSK671 | DSK6711 | EDM | EDMA | EMIF | Emulator | EVM | EVM620 | FFT | FIR | GPIO | Halting | HPI | HWI | IDK | JTAG | LDB | LDH | LDW | Linker | LMS | LOG_printf | Matlab | McBSP | MEM_alloc | MIPS | PCI | PCM3003 | Pipeline | Profiling | QDM | Reset | ROM | RTDX | Sampling | SDRAM | Stack | TEB | THS1206 | TMS320C621 | TMS320C6416 | TMS320C6711 | TMS320C6713 | UART | Vector Table | XBUS | XDS560

dear all,
 
as i know, the local memory inside DM642 and DAVINCI DM6446 can be set to be
cache or to be local SRAM.
 
i want to if set to be local SRAM, is this SRAM single-ported or dual-ported?
 
actually, i am just curious about whether the external DMA engine and processor
core can access this local SRAM simultaneously, i.e., if DMA engine and
processor core acess the local SRAM simultaneously but with different address,
will one of them defer the access from the other?  
e.g., during DMA engine is accessing the local SRAM, if processor issue a data
access instruction which targets this local SRAM, the pipeline will be stalled
until DMA engine release the memory control?

any reply is apprepriated!
 
br,
zhouxiao
 
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