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We are using Tms320C6211 DSP under 8 bit ROM boot configuration CE1 space,ie HD[3]-HD[4] being {1,0}. Iam testing the CE1, Data Bus and Address bus of ROM I have the following observations. (1) Once I make the #RST low , the CE1 and Address bus of the ROM remain high and Data bus remain low. (2) Once I remove the #RST , I find CE1 going low and then high , while the the status on ROM address bus goes low but thers no change in the status of Data bus As the DSP makes a load of 1k from the ROM to the on -chip memory the address and data bus should pulse to make the necessary load, but thats not happening. Pls provide some valuable suggestions in this regard. Also provide some info abt the reading material regarding the BOOT PROM and writing the linker files for the same.

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